FinFET with improved SEU performance

A finFET comprising:

• a substrate of semiconductor material;
• a first well region formed in the substrate and having p-type conductivity;
• a plurality of first thin segments of the semiconductor material integral with the first well region and extending in a first direction away from the substrate, each first thin segment extending lengthwise in a second direction with a channel between adjacent first thin segments;
• a transistor formed on each of at least two adjacent first thin segments, each transistor having source and drain regions and a gate;
• at least one elongated first trapping region located in or on the substrate between two adjacent first thin segments, at least one of the elongated first trapping regions having n-type conductivity and being coupled to a well region having n-type conductivity;
• a second well region formed in the substrate and having n-type conductivity;
• a plurality of second thin segments of the semiconductor material integral with the second well region and extending in the first direction away from the substrate, each second thin segment extending lengthwise in the second direction with a channel between adjacent second thin segments;
• a transistor formed on each of at least two adjacent second thin segments, each transistor having source and drain regions and a gate;
• and
• at least one elongated second trapping region located in or on the substrate between two adjacent second thin segments, at least one of the elongated second trapping regions having p-type conductivity and being coupled to a well region having p-type conductivity.

A method for forming a finFET comprising:

• forming a plurality of first thin semiconductor segments that are integral with a semiconductor substrate having a first conductivity type and are spaced apart by first channels;
• forming in or on the substrate at a bottom of at least one first channel a first trapping region, by epitaxially growing on the substrate a region having a second conductivity-type opposite the first conductivity-type;
• and
• forming in at least one first thin segment a transistor having source and drain regions and a gate.