US 9,543,379 B2Granted

Semiconductor device with peripheral breakdown protection

AssigneeNXP USA, Inc.

InventorsHongning Yang, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo

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Abstract

A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.

Claims18

Dependent claims

A device comprising:

a semiconductor substrate;
source and drain regions disposed in the semiconductor substrate and having a first conductivity type;
a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed;
a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions;
a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region;
and
a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type;
wherein the breakdown protection region comprises an electrically floating well disposed between the device isolation region and the body region;
wherein the breakdown protection region has a width at a surface of the semiconductor substrate in a lateral direction that establishes a spacing between the body region and the device isolation region, the width falling in a range from 1.0 microns to 2.0 microns so that the breakdown protection region improves a breakdown voltage level of the device by preventing charge inversion from occurring in the body region along the device isolation region;
and
wherein the first conductivity type is p-type and the second conductivity type is n-type.

8 more elements

An electronic apparatus comprising:

a semiconductor substrate;
and
a transistor disposed in the semiconductor substrate and comprising:
first and second semiconductor regions having a first conductivity type;
a third semiconductor region having a second conductivity type and through which current flows between the first and second semiconductor regions during operation;
a device isolation region laterally surrounding the first, second, and third semiconductor regions;
a breakdown protection region disposed between the device isolation region and the third semiconductor region and having the first conductivity type;
and
a buried layer extending laterally across the first semiconductor region, the second semiconductor region, and the third semiconductor region and having the second conductivity type;
wherein the breakdown protection region has a width at a surface of the semiconductor substrate in a lateral direction that establishes a spacing between the third semiconductor region and the device isolation region, the width falling in a range from 1.0 microns to 2.0 microns so that the breakdown protection region improves a breakdown voltage level of the transistor by preventing charge inversion from occurring in the third semiconductor region along the device isolation region;
wherein the breakdown protection region is electrically floating;
and
wherein the first conductivity type is p-type and the second conductivity type is n-type.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/218,330Filed 18 Mar 2014
Published: US 2015/0270333 A124 Sep 2015
Granted: 10 Jan 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification27 codes

H10D 62/109
By having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination…
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/0281
Of double-diffused metal oxide semiconductor [DMOS] FETs: of lateral dmos [ldmos] fets
H10D 30/0285
Of lateral dmos [ldmos] fets: using formation of insulating sidewall spacers