Semiconductor memory device and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorsKazuaki Nakajima, Seiichi Omoto, Hiroshi Toyoda
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Abstract
A semiconductor memory device according to an embodiment comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a slit portion. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer has one end thereof connected to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The slit portion extends in a direction of the substrate from a surface of the stacked body, wherein the slit portion has its longitudinal direction in a direction intersecting the first direction.
Claims18
A semiconductor memory device, comprising:
- a plurality of stacked bodies including a plurality of control gate electrodes stacked above a substrate, the plurality of stacked bodies having their longitudinal direction in a first direction parallel to the substrate and being arranged in a second direction intersecting the first direction;
- a semiconductor layer having one end thereof connected to the substrate, the semiconductor layer facing the plurality of control gate electrodes;
- a charge accumulation layer positioned between the control gate electrode and the semiconductor layer;
- and
- a slit portion extending in a direction of the substrate from a surface of the stacked body, wherein
- the slit portion has its longitudinal direction in a direction intersecting the first direction.
A semiconductor memory device, comprising:
- a plurality of stacked bodies including a plurality of control gate electrodes stacked above a substrate, the plurality of stacked bodies having their longitudinal direction in a first direction parallel to the substrate and being arranged in a second direction intersecting the first direction;
- a semiconductor layer having one end thereof connected to the substrate, the semiconductor layer facing the plurality of control gate electrodes;
- a charge accumulation layer positioned between the control gate electrode and the semiconductor layer;
- and
- a plurality of slit portions extending in a direction of the substrate from a surface of the stacked body, wherein
- the plurality of slit portions are disposed so as to be aligned in a direction intersecting the first direction.
A method of manufacturing a semiconductor memory device, comprising:
- alternately stacking a plurality of inter-layer insulating layers and sacrifice layers above a substrate to form a stacked body;
- forming a first through hole in the stacked body, the first through hole penetrating the stacked body;
- forming a first semiconductor layer inside the first through hole, the first semiconductor layer facing the stacked body;
- forming a second through hole in the stacked body, the second through hole penetrating the stacked body in a direction from a surface of the stacked body to the substrate and having longitudinal direction in a first direction parallel to the substrate, thereby dividing the stacked body;
- removing the sacrifice layer via the second through hole;
- and
- forming a conductive layer in a cavity portion after the sacrifice layer has been removed.
Dependencies are inferred from the claim text.