Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors

A method of fabricating a memory device, comprising:

• forming an alternating stack of insulator layers and spacer material layers over a single crystalline semiconductor surface of a substrate;
• forming stepped surfaces by patterning the alternating stack, wherein the single crystalline semiconductor surface is exposed in a region from which all layers of the alternating stack are removed;
• after forming the stepped surfaces, forming an epitaxial semiconductor pedestal and a dielectric material portion over a semiconductor surface of the semiconductor substrate and over the stepped surfaces, respectively, wherein the epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor surface of the substrate;
• forming an array of memory stack structures through a remaining portion of the alternating stack;
• and
• forming at least one semiconductor device on the epitaxial semiconductor pedestal,
• wherein the dielectric material portion is formed by deposition and patterning of a dielectric material prior to formation of the epitaxial semiconductor pedestal, and
• wherein the epitaxial semiconductor pedestal is formed by:
• performing a first epitaxial semiconductor deposition process that forms a lower epitaxial semiconductor pedestal portion;
• and
• performing a second epitaxial semiconductor deposition process that forms an upper epitaxial semiconductor pedestal portions, wherein the lower and upper epitaxial semiconductor pedestal portions collectively constitute the epitaxial semiconductor pedestal.

A method of fabricating a memory device, comprising:

• forming an alternating stack of insulator layers and spacer material layers over a single crystalline semiconductor surface of a substrate;
• forming a planarization stopping layer over the alternating stack;
• forming stepped surfaces by patterning the alternating stack, wherein the single crystalline semiconductor surface is exposed in a region from which all layers of the alternating stack are removed;
• after forming the stepped surfaces, forming an epitaxial semiconductor pedestal and a dielectric material portion over a semiconductor surface of the semiconductor substrate and over the stepped surfaces, respectively, wherein the epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor surface of the substrate;
• planarizing a topmost surface of the epitaxial semiconductor pedestal employing the planarization stopping layer as a stopping layer;
• forming an array of memory stack structures through a remaining portion of the alternating stack;
• and
• forming at least one semiconductor device on the epitaxial semiconductor pedestal.

A method of fabricating a memory device, comprising:

• forming an alternating stack of insulator layers and spacer material layers over a single crystalline semiconductor surface of a substrate;
• forming steeped surfaces by patterning the alternating stack, wherein the single crystalline semiconductor surface is exposed in a region from which all layers of the alternating stack are removed;
• after forming the stepped surfaces, forming an epitaxial semiconductor pedestal and a dielectric material portion over a semiconductor surface of the semiconductor substrate and over the stepped surfaces, respectively, wherein the epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor surface of the substrate;
• forming an array of memory stack structures through a remaining portion of the alternating stack;
• and
• forming at least one semiconductor device on the epitaxial semiconductor pedestal;
• forming a plurality of dummy openings through the stepped surfaces;
• forming a plurality of dummy memory stack structures in the plurality of dummy openings at the same time as forming the array of memory stack structures;
• and
• forming a plurality of bit lines in electrical contact with the array of memory stack structures, such that the plurality of dummy memory stack structures are not in electrical contact with the plurality of bit lines,
• wherein each of the memory stack structures comprises:
• a memory film including tunneling dielectric, at least one charge storage region and a blocking dielectric;
• and
• a vertical semiconductor channel contacting an inner surface of the memory film and overlying the single crystalline semiconductor surface of the substrate.

A method of fabricating a memory device, comprising:

• forming an alternating stack of insulator layers and spacer material layers over a single crystalline semiconductor surface of a substrate;
• forming stepped surfaces by patterning the alternating stack, wherein the single crystalline semiconductor surface is exposed in a region from which all layers of the alternating stack are removed;
• after forming the stepped surfaces, forming an epitaxial semiconductor pedestal and a dielectric material portion over a semiconductor surface of the semiconductor substrate and over the stepped surfaces, respectively, wherein the epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor surface of the substrate;
• forming an array of memory stack structures through a remaining portion of the alternating stack;
• and
• forming at least one semiconductor device on the epitaxial semiconductor pedestal, wherein:
• the memory device comprises a monolithic three-dimensional NAND memory device;
• the substrate comprises a silicon substrate;
• the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
• at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings;
• the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
• and
• each NAND string comprises:
• a semiconductor channels, wherein at least one end portion the semiconductor channel extends substantially perpendicular to a top surface of the silicon substrate;
• a plurality of charge storage elements, each charge storage element located adjacent to a respective semiconductor channel;
• and
• a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the semiconductor substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

A memory device, comprising:

• an alternating stack of electrically conductive layers and insulator layers located over a semiconductor substrate;
• an array of memory stack structures located within memory openings which extend through the alternating stack;
• a dielectric material portion overlying stepped surfaces of the alternating stack;
• an epitaxial semiconductor pedestal having substantially vertical sidewalls in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate;
• and
• at least one semiconductor device located on the top surface of the epitaxial semiconductor pedestal;
• wherein:
• the epitaxial semiconductor pedestal has top surface within a same horizontal plane as a top surface of the dielectric material portion;
• an entire contact area between the dielectric material portion and the epitaxial semiconductor pedestal is within a same vertical plane;
• the substantially vertical sidewalls of the epitaxial semiconductor pedestal lack stepped surfaces;
• and
• the at least one semiconductor device comprises field effect transistor of a driver circuit of the memory device located in a peripheral region of the memory device.

A memory device, comprising:

• an alternating stack of electrically conductive layers and insulator layers located over a semiconductor substrate;
• an array of memory stack structures located within memory openings which extend through the alternating stack;
• a dielectric material portion overlying stepped surfaces of the alternating stack;
• an epitaxial semiconductor pedestal having substantially vertical sidewalls in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate;
• and
• at least one semiconductor device located on the top surface of the epitaxial semiconductor pedestal,
• wherein the epitaxial semiconductor pedestal comprises an upper epitaxial semiconductor pedestal portion and a lower epitaxial semiconductor pedestal portion that comprises a different semiconductor material than the upper semiconductor pedestal portion.

A memory device, comprising:

• an alternating stack of electrically conductive layers and insulator layers located over a semiconductor substrate;
• an array of memory stack structures located within memory openings which extend through the alternating stack;
• a dielectric material portion overlying stepped surfaces of the alternating stack;
• an epitaxial semiconductor pedestal having substantially vertical sidewalls in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate;
• at least one semiconductor device located on the top surface of the epitaxial semiconductor pedestal;
• contact via structures extending through the dielectric material portions and contacting a respective electrically conductive layer;
• a plurality of dummy openings extending through the stepped surfaces;
• a plurality of dummy memory stack structures located in the plurality of dummy openings;
• and
• a plurality of bit lines in electrical contact with the array of memory stack structures,
• wherein the plurality of dummy memory stack structures are not in electrical contact with the plurality of bit lines.

A memory device, comprising:

• an alternating stack of electrically conductive layers and insulator layers located over a semiconductor substrate;
• an array of memory stack structures located within memory openings which extend through the alternating stack;
• a dielectric material portion overlying stepped surfaces of the alternating stack;
• an epitaxial semiconductor pedestal having substantially vertical sidewalls in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate:
• at least one semiconductor device located on the top surface of the epitaxial semiconductor pedestal
• the memory device comprises a monolithic three-dimensional NAND memory device;
• the semiconductor substrate comprises a silicon substrate;
• the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
• at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings;
• the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
• and
• each NAND string comprises:
• a semiconductor channels, wherein at least one end portion the semiconductor channel extends substantially perpendicular to a top surface of the silicon substrate;
• a plurality of charge storage elements, each charge storage element located adjacent to a respective semiconductor channel;
• and
• a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the semiconductor substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.