US 9,543,315 B1Granted

Semiconductor device

AssigneeRenesas Electronics Corporation

InventorsHiraku Chakihara, Satoshi Abe

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Abstract

The memory cell includes a gate insulating film, a control gate electrode, a cap insulating film, a cap layer, another gate insulating film, and a memory gate electrode. A laminated capacitive element includes a capacitive electrode which is constituted by a sub-electrode and another sub-electrode formed of mesa portions (protruding portions) disposed on the sub-electrode at a predetermined interval and each having an upper surface and side surfaces, a capacitive insulating film which is formed along an upper surface of the sub-electrode and the upper surface and the side surfaces of the another sub-electrode, and another capacitive electrode which is formed on the capacitive insulating film. Further, the control gate electrode and the sub-electrode are made of a conductor film, the cap layer and the another sub-electrode are made of other conductor film, and the memory gate electrode and the another capacitive electrode are made of another conductor film.

Claims15

Dependent claims

A semiconductor device comprising:

a memory cell formed in a first region of a semiconductor substrate;
and
a capacitive element formed in a second region of the semiconductor substrate,
wherein the memory cell includes:
a first conductor piece disposed on a main surface of the semiconductor substrate via a first insulator piece;
a second conductor piece disposed on the first conductor piece via a second insulator piece;
a third conductor piece disposed on the main surface of the semiconductor substrate via a third insulator piece, and disposed on side surfaces of the first conductor piece and the second conductor piece via a fourth insulator piece;
and
a pair of semiconductor regions formed in the main surface of the semiconductor substrate such that the first conductor piece and the third conductor piece are interposed therebetween,
wherein the capacitive element includes:
a fourth conductor piece formed on the main surface of the semiconductor substrate and having an upper surface;
a plurality of mesa-like fifth conductor pieces disposed on the fourth conductor piece via a fifth insulator piece, and each having an upper surface and side surfaces on the fourth conductor piece;
a sixth insulator piece disposed on the upper surface of the fourth conductor piece and on the side surfaces of each of the fifth conductor pieces;
and
a sixth conductor piece disposed between the neighboring fifth conductor pieces via the sixth insulator piece,
wherein the first conductor piece and the fourth conductor piece are made of a first conductor film,
wherein the second conductor piece and the fifth conductor pieces are made of a second conductor film, and
wherein the third conductor piece and the sixth conductor piece are made of a third conductor film.

15 more elements

A semiconductor device comprising:

a memory cell formed in a first region of a semiconductor substrate;
a capacitive element formed in a second region of the semiconductor substrate;
and
a MISFET formed in a third region of the semiconductor substrate,
wherein the memory cell includes:
a first conductor piece disposed on a main surface of the semiconductor substrate via a first insulator piece;
a second conductor piece disposed on the first conductor piece via a second insulator piece;
a third conductor piece disposed on the main surface of the semiconductor substrate via a third insulator piece, and disposed on side surfaces of the first conductor piece and the second conductor piece via a fourth insulator piece;
and
a pair of first semiconductor regions formed in the main surface of the semiconductor substrate such that the first conductor piece and the third conductor piece are interposed therebetween,
wherein the capacitive element includes:
a fourth conductor piece formed on the main surface of the semiconductor substrate and having an upper surface;
a plurality of mesa-like fifth conductor pieces disposed on the fourth conductor piece via a fifth insulator piece, and each having an upper surface and side surfaces on the fourth conductor piece;
a sixth insulator piece disposed on the upper surface of the fourth conductor piece and on the side surfaces of each of the fifth conductor pieces;
and
a sixth conductor piece disposed between the neighboring fifth conductor pieces via the sixth insulator piece,
wherein the MISFET includes:
a seventh conductor piece disposed on the semiconductor substrate via a seventh insulator piece;
and
a pair of second semiconductor regions formed in the main surface of the semiconductor substrate such that the seventh conductor piece is interposed therebetween,
wherein the first conductor piece, the fourth conductor piece, and the seventh conductor piece are made of a first conductor film,
wherein the second conductor piece and the fifth conductor piece are made of a second conductor film,
wherein the third conductor piece and the sixth conductor piece are made of a third conductor film, and
wherein the second insulator piece and the fifth insulator piece are made of a first insulating film.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/212,331Filed 18 Jul 2016
Priority: JP 2015-15889011 Aug 2015
Granted: 10 Jan 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
H10D 1/047
Of capacitors having potential barriers, e.g. varactors: of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
H10D 84/811
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs: combinations of…
H10D 84/813
Combinations of field-effect devices and one or more diodes, capacitors or resistors: combinations of field-effect devices and capacitor only