Manufacturing method of semiconductor device and semiconductor device
AssigneeRenesas Electronics Corporation
InventorTatsuyoshi Mihara
Life of this patent
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Abstract
A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect to the control gate electrode is provided which improves its performance. A control gate electrode which configures a memory cell, and a metallic film which configures part of the memory gate electrode are formed by a so-called gate last process. Thus, the memory gate electrode is configured by a silicon film corresponding to a p-type semiconductor film being in contact with an ONO film, and the metallic film. Further, a contact plug is coupled to both of the silicon film and the metallic film which configure the memory gate electrode.
Claims16
A method of manufacturing a semiconductor device equipped with a memory cell of a nonvolatile memory, comprising the steps of:
- (a) providing a semiconductor substrate;
- (b) forming a first dummy gate electrode over the semiconductor substrate through a first insulating film;
- (c) forming in order a second insulating film having a charge accumulation part there inside, a first semiconductor film and a second semiconductor film each having a p-type conductivity type, so as to cover sidewalls of the first dummy gate electrode and the semiconductor substrate exposed from the first insulating film in adjacency to the sidewalls;
- (d) processing the first semiconductor film and the second semiconductor film to thereby form a second dummy gate electrode including the first semiconductor film and the second semiconductor film over the sidewalls of the first dummy gate electrode through the second insulating film;
- (e) forming a first interlayer insulating film so as to cover the first dummy gate electrode and the second dummy gate electrode;
- (f) polishing the first interlayer insulating film to expose the first dummy gate electrode and the second dummy gate electrode;
- (g) removing the second semiconductor film configuring the second dummy gate electrode, and the first dummy gate electrode;
- (h) forming a first gate electrode corresponding to a metal gate electrode for the memory cell in a first trench corresponding to a region from which the first dummy gate electrode is removed in the (g) step, and forming a metallic film in a second trench corresponding to a region from which the second semiconductor film is removed in the (g) step to thereby form a second gate electrode including the first semiconductor film and the metallic film for the memory cell.
A semiconductor device, comprising:
- a semiconductor substrate;
- and
- a memory cell including:
- a first gate electrode corresponding to a metal gate electrode, the first gate electrode being formed over the semiconductor substrate through a first insulating film,
- a second gate electrode formed over one of sidewalls of the first gate electrode through a second insulating film having a charge accumulation part there inside, and
- source-drain regions formed in a main surface of the semiconductor substrate,
- wherein the second gate electrode is formed over the semiconductor substrate through the second insulating film,
- wherein the second gate electrode includes a metallic film and further includes a first semiconductor film having a p-type conductivity, which is continuously formed from an area between the metallic film and the first gate electrode to between the metallic film and the semiconductor substrate,
- wherein a first high permittivity insulating film higher in permittivity than silicon nitride is interposed between the metallic film and the first semiconductor film, and
- wherein a contact plug electrically coupled to the metallic film and the first semiconductor film is formed over the memory cell.
Dependencies are inferred from the claim text.