Nonvolatile memory device and method for fabricating the same

A method for fabricating a nonvolatile memory device, the method comprising:

• forming a first interlayer dielectric layer over a substrate;
• forming a stack structure in which a plurality of sacrificial layers and a plurality of second interlayer dielectric layers are alternately stacked over the first interlayer dielectric layer;
• forming a third interlayer dielectric layer over an uppermost sacrificial layer of the plurality of sacrificial layers;
• forming a hole in the first, second and third interlayer dielectric layers and the sacrificial layers, the hole exposing the first, second and third interlayer dielectric layers, the sacrificial layers, and the substrate;
• etching the first, second and third interlayer dielectric layers, exposed through the hole, to form a plurality of grooves in the first, second and third interlayer dielectric layers;
• and
• sequentially forming a charge blocking layer and a floating gate electrode in each of the plurality of grooves,
• wherein the first and third interlayer dielectric layers have a lower etch rate than the plurality of second interlayer dielectric layers,
• wherein sequentially forming the charge blocking layer and the floating gate electrode, in each of the plurality of grooves, further comprises:
• forming a first floating gate electrode, having a first width, in the grooves formed in the first and third interlayer dielectric layers;
• and
• forming a second floating gate electrode, having a second width that is greater than the first width, in each of the grooves formed in the plurality of second interlayer dielectric layers.

A method for fabricating a nonvolatile memory device, the method comprising:

• forming a first interlayer dielectric layer over a substrate;
• forming a stack structure in which a plurality of sacrificial layers and a plurality of second interlayer dielectric layers are alternately stacked over the first interlayer dielectric layer;
• forming a third interlayer dielectric layer over an uppermost sacrificial layer of the plurality of sacrificial layers;
• forming a hole in the first, second and third interlayer dielectric layers and the sacrificial layers, the hole exposing the first, second and third interlayer dielectric layers, the sacrificial layers, and the substrate;
• etching the first, second and third interlayer dielectric layers, exposed through the hole, to form a plurality of grooves in the first, second and third interlayer dielectric layers;
• and
• sequentially forming a plurality of charge blocking layers and a plurality of floating gate electrodes in the plurality of grooves, respectively,
• wherein the first and third interlayer dielectric layers have a lower etch rate than the plurality of second interlayer dielectric layers,
• wherein a lowermost floating gate electrode of the plurality of floating gate electrodes is positioned at a lowermost part of the stack structure and an uppermost floating gate electrode of the plurality of floating gate electrodes is positioned at an uppermost part of the stack structure, and each of the plurality of floating gate electrodes has a constant thickness, in a direction perpendicular to a surface of the substrate, throughout its left edge to its right edge, and the lowermost and the uppermost floating gate electrodes have a smaller horizontal width in a direction parallel to the surface of the substrate, than a horizontal width of each of the plurality of floating gate electrodes between the lowermost and the uppermost floating gate electrodes.