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US 9,543,311 B2Granted
Vertical memory cell with non-self-aligned floating drain-source implant
AssigneeSTMicroelectronics (Rousset) SAS
InventorsMarc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau
Life of this patent
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Abstract
Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
Claims18
A memory cell, comprising:
- a semiconductor substrate having a trench;
- a selection gate extending in the trench in the substrate;
- a floating gate on the substrate;
- a control gate on the floating gate;
- an electrically floating doped region implanted at an intersection of a vertical channel region extending along the selection gate and a horizontal channel region extending along the floating gate, the floating gate overlapping the electrically floating doped region and a portion of the selection gate by a non-zero overlap distance.
2 more elements
A device, comprising:
- a semiconductor substrate having a trench;
- a plurality of memory cells arranged in pairs of memory cells, each pair of memory cells including:
- a shared selection gate extending in the trench in the substrate;
- first and second control gates;
- first and second floating gates on the substrate, the first and second control gates being on the first and second floating gates, respectively, the first and second floating gates overlapping a portion of the shared selection gate by a non-zero overlap distance;
- and
- first and second electrically floating doped regions, the first electrically floating doped regions being implanted at a first intersection of a first vertical channel region extending along a first side of the selection gate and a first horizontal channel region extending along the first floating gate, the second electrically floating doped region being implanted at a second intersection of a second vertical channel region extending along a second side of the selection gate and a second horizontal channel region extending along the second floating gate.
4 more elements
A device, comprising:
- a semiconductor substrate having a trench;
- a first memory cell on the substrate on a first side of the trench and a second memory cell on the substrate on a second side of the trench, each memory cell including:
- a selection gate positioned in the trench;
- a floating gate on the substrate and on a portion of the selection gate;
- a control gate on the floating gate;
- and
- a first indentation in the substrate at a boundary of the first side of the trench and the substrate and a second indentation in the substrate at a boundary of the second side of the trench and the substrate, a portion of each floating gate extending into the first or second indentation;
- and
- first and second doped regions implanted in the substrate, the first and second doped regions being positioned adjacent to the first and second indentations, respectively, the floating gate overlapping the first or second doped region.
6 more elements
Dependencies are inferred from the claim text.