Vertical memory devices and methods of manufacturing the same

A method of manufacturing a vertical memory device, the method comprising:

• providing a substrate, the substrate including a cell array region and a peripheral circuit region;
• forming a mold structure on the cell array region of the substrate such that the peripheral circuit region of the substrate remains exposed, the mold structure having a first portion and a second portion integrally connected to the first portion, the second portion having a plurality of steps;
• forming an insulating layer on the second portion of the mold structure and on the peripheral circuit region of the substrate;
• forming a common source line opening, the common source line opening extending through the first portion and the second portion of the mold structure in a first direction, the first direction being perpendicular to an upper surface of the substrate;
• forming a plurality of cell gate line contact holes extending through the insulating layer in the first direction to the plurality of steps, each of the plurality of steps being exposed by at least one of the cell gate line contact holes;
• forming a peripheral circuit contact hole extending through the insulating layer on the peripheral circuit region, the peripheral circuit contact hole extending in the first direction;
• and
• simultaneously forming a common source line contact plug in the common source line opening, a plurality of cell gate line contact plugs in the plurality of cell gate line contact holes, and a peripheral circuit contact plug in the peripheral circuit contact hole,
• wherein an upper surface of the first contact plug is substantially coplanar with upper surfaces of the cell gate line contact plugs and upper surface of the peripheral circuit contact plug.