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US 9,543,304 B2Granted
Vertical junction FinFET device and method for manufacture
AssigneeSTMicroelectronics S.r.l.
InventorsQing Liu, John Hongguang Zhang
Life of this patent
Estimating the term…
Abstract
A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.
Claims25
An integrated circuit transistor device, comprising:
- a semiconductor substrate;
- a region within the semiconductor substrate doped with a first conductivity-type dopant;
- a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the first conductivity-type dopant;
- a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the first conductivity-type dopant;
- and
- a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with a second conductivity-type dopant.
3 more elements
An integrated circuit, comprising:
- a semiconductor substrate;
- a first region within the semiconductor substrate doped with a first conductivity-type dopant;
- a second region within the semiconductor substrate doped with a second conductivity-type dopant;
- a first fin of semiconductor material having a first end in contact with said first region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said first fin doped with the first conductivity-type dopant;
- a second fin of semiconductor material having a first end in contact with said second region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said second fin doped with the second conductivity-type dopant;
- a first epitaxial region in contact with the second end of the first fin of semiconductor material, said first epitaxial region doped with the first conductivity-type dopant;
- a second epitaxial region in contact with the second end of the second fin of semiconductor material, said second epitaxial region doped with the second conductivity-type dopant;
- a third epitaxial region in contact with sidewalls of the first fin of semiconductor material, said third epitaxial region doped with the second conductivity-type dopant;
- and
- a fourth epitaxial region in contact with sidewalls of the second fin of semiconductor material, said fourth epitaxial region doped with the first conductivity-type dopant.
7 more elements
An integrated circuit transistor device, comprising:
- a semiconductor substrate;
- a region within the semiconductor substrate doped with an n-type conductivity-type dopant;
- a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the n-type conductivity-type dopant;
- a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the n-type conductivity-type dopant;
- and
- a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with a p-type conductivity-type dopant;
- wherein the region, fin, first epitaxial region and second epitaxial region form a vertical junction field effect transistor.
4 more elements
An integrated circuit transistor device, comprising:
- a semiconductor substrate;
- a region within the semiconductor substrate doped with a p-type conductivity-type dopant;
- a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the p-type conductivity-type dopant;
- a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the p-type conductivity-type dopant;
- and
- a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with an n-type conductivity-type dopant;
- wherein the region, fin, first epitaxial region and second epitaxial region form a vertical junction field effect transistor.
4 more elements
An integrated circuit transistor device, comprising:
- a semiconductor substrate;
- a region within the semiconductor substrate doped with a first conductivity-type dopant;
- a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the first conductivity-type dopant;
- a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the first conductivity-type dopant;
- and
- a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with a second conductivity-type dopant;
- wherein the integrated circuit transistor device is a junction field effect transistor (JFET) device with said second epitaxial region comprising a gate structure, said region within the semiconductor substrate comprising a source region and said first epitaxial region comprising a drain region.
4 more elements
Dependencies are inferred from the claim text.