US 9,543,300 B2Granted

CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device

AssigneeSamsung Electronics Co., Ltd.

InventorsHye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Yu-Gyun Shin, Sug-Hun Hong, Hoon-Joo Na, Hyung-Seok Hong

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Abstract

Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

Claims30

Dependent claims

A semiconductor device comprising:

a substrate including a first region doped with a first conductivity type impurity and a second region doped with a second conductivity type impurity;
a first insulating layer disposed on the substrate and including a first trench in the first region and a second trench in the second region;
a first gate insulating layer disposed in the first trench;
a first metal nitride layer disposed on the first gate insulating layer;
a first concave-shaped metal containing layer disposed on the first metal nitride layer;
a second concave-shaped metal containing layer disposed on the first concave-shaped metal containing layer;
a first filling layer disposed on the second concave-shaped metal containing layer;
a first capping layer disposed on a top surface of the first filling layer, on a top surface of the first concave-shaped metal containing layer, and on a top surface of the second concave-shaped metal containing layer in the first trench and filling the first trench;
a second gate insulating layer disposed in the second trench;
a second metal nitride layer disposed on the second gate insulating layer;
a third concave-shaped metal containing layer disposed on the second metal nitride layer;
a second filling layer disposed on the third concave-shaped metal containing layer;
and
a second capping layer disposed on a top surface of the second filling layer and on a top surface of the third concave-shaped metal containing layer in the second trench and filling the second trench,
wherein a bottom surface of the first filling layer is disposed higher than a bottom surface of the second filling layer,
the first capping layer includes a material having an etching rate different from that of the first insulating layer, and
the second capping layer includes a material having an etching rate different from that of the first insulating layer.

14 more elements

A semiconductor device comprising:

a substrate including a first region doped with a first conductivity type impurity and a second region doped with a second conductivity type impurity;
an insulating layer disposed on the substrate and including a first trench in the first region and a second trench in the second region;
a first gate insulating layer disposed in the first trench;
a first metal nitride layer disposed on the first gate insulating layer;
a first concave-shaped metal containing layer disposed on the first metal nitride layer;
a second concave-shaped metal containing layer disposed on the first concave-shaped metal containing layer;
a first filling layer disposed on the second concave-shaped metal containing layer;
a first capping layer disposed on a top surface of the first filling layer, on a top surface of the first concave-shaped metal containing layer, and on a top surface of the second concave-shaped metal containing layer in the first trench and filling the first trench;
a second gate insulating layer disposed in the second trench;
a second metal nitride layer disposed on the second gate insulating layer;
a third concave-shaped metal containing layer disposed on the second metal nitride layer;
a second filling layer disposed on the third concave-shaped metal containing layer;
and
a second capping layer disposed on a top surface of the second filling layer and on a top surface of the third concave-shaped metal containing layer in the second trench and filling the second trench,
wherein a bottom surface of the first filling layer is disposed higher than a bottom surface of the second filling layer, and
a top surface of the insulating layer is coplanar with a top surface of the first capping layer and with a top surface of the second capping layer.

13 more elements

A semiconductor device comprising:

a substrate;
a first insulating layer disposed on the substrate and including a trench;
a gate insulating layer disposed in the trench;
a metal nitride layer disposed on the gate insulating layer;
a first concave-shaped metal containing layer disposed on the metal nitride layer, and including a bottom portion, a first sidewall and a second sidewall;
a second concave-shaped metal containing layer disposed on the first concave-shaped metal containing layer;
a filling layer disposed on the second concave-shaped metal containing layer;
and
a capping layer disposed on a top surface of the filling layer, on a top surface of the first concave shaped metal containing layer and on a top surface of the second concave-shaped metal containing layer in the trench and filling the trench,
wherein the second concave-shaped metal containing layer is not formed on an upper surface of the first sidewall of the first concave-shaped metal containing layer and not formed on an upper surface of the second sidewall of the first concave-shaped metal containing layer, and
the capping layer includes a material having an etching rate different from that of the first insulating layer.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/054,571Filed 26 Feb 2016 · continuation
Priority: KR 10-2010-000655325 Jan 2010
Published: US 2016/0204108 A114 Jul 2016
Granted: 10 Jan 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
H10D 1/66
Capacitors having potential barriers: conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
H10D 64/518
Characterised by the conducting layers: characterised by their lengths or sectional shapes
H10D 64/667
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor comprising a layer of…

Family

Application12/972,961Parent of this continuation · filed 20 Dec 2010
US 2016/0204108 A1Pre-grant publication · published 14 Jul 2016
US 9,287,199 B2Parent of this continuation
US 2011/0180879 A1Published application
US 9,543,300 B2This patent

From the US filing history. Foreign family members aren’t listed.