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US 9,543,276 B2Granted
Chip-stacked semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-kun Jee, Tae-hong Min, Sun-kyoung Seo
Life of this patent
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Abstract
A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided.
Claims13
A chip-stacked semiconductor package comprising:
- a first chip including a plurality of first real bump pads and a plurality of first dummy bump pads;
- a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads;
- and
- a sealing member sealing the first chip and the second chip.
1 more element
Dependencies are inferred from the claim text.