US 9,543,246 B2 · Semiconductor device

Abstract

One semiconductor device includes one parallel transistor for connecting in parallel multiple vertical transistors disposed in an active region on a semiconductor substrate. The parallel transistor includes semiconductor pillars that project out in a direction perpendicular to a main surface of the semiconductor substrate; a lower diffusion layer that is disposed below the semiconductor pillars; upper diffusion layers that are each disposed on an upper section of the semiconductor pillars; and gate electrodes disposed, with a gate insulator film therebetween, on the entire side surfaces of the semiconductor pillars. The upper diffusion layers are connected to one upper contact plug that is disposed over the upper diffusion layers.

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Drawings

Claims14

Dependent claims

A semiconductor device comprising one parallel transistor in which a plurality of vertical transistors disposed in an active region on a semiconductor substrate are connected in parallel, wherein the parallel transistor comprises:

a plurality of semiconductor pillars protruding out in a direction perpendicular to a main surface of the semiconductor substrate;
a lower diffusion layer disposed below the plurality of semiconductor pillars;
a plurality of upper diffusion layers, disposed respectively at the top of the plurality of semiconductor pillars;
and
a gate electrode disposed over the side surfaces, in their entirety, of the plurality of semiconductor pillars, with the interposition of a gate insulating film;
and wherein the plurality of upper diffusion layers are connected to one upper contact plug disposed on the plurality of upper diffusion layers, and wherein the one upper contact plug is connected to a wiring line disposed on the one upper contact plug.

3 more elements

A semiconductor device comprising:

an element isolation region disposed in a main surface of a semiconductor substrate;
a first active region and a second active region which are enclosed by the element isolation region and are adjacent to one another in a first direction;
and
an intermediate element isolation region sandwiched between the first active region and the second active region;
wherein the first active region comprises:
a first semiconductor pillar adjacent to the intermediate element isolation region;
a first upper diffusion layer located at the top of the first semiconductor pillar;
a second semiconductor pillar adjacent, in the first direction, to the first semiconductor pillar;
a second upper diffusion layer located at the top of the second semiconductor pillar;
a continuous first gate electrode enclosing the peripheries of the first semiconductor pillar and the second semiconductor pillar;
a first lower diffusion layer disposed below the first and second semiconductor pillars;
the second active region comprises:
a third semiconductor pillar adjacent to the intermediate element isolation region;
a third upper diffusion layer located at the top of the third semiconductor pillar;
a fourth semiconductor pillar adjacent, in the first direction, to the third semiconductor pillar;
a fourth upper diffusion layer located at the top of the fourth semiconductor pillar;
a continuous second gate electrode enclosing the peripheries of the third semiconductor pillar and the fourth semiconductor pillar;
a second lower diffusion layer disposed below the third and fourth semiconductor pillars, wherein the first and second lower diffusion layers are connected respectively to first and second lower contact plugs;
and
the intermediate element isolation region comprises:
a dummy pillar extending in the first direction, spanning between the first active region and the second active region;
and
a power-feed gate electrode enclosing the periphery of the dummy pillar;
the first gate electrode and the second gate electrode are each connected to the power-feed gate electrode;
the first upper diffusion layer and the second upper diffusion layer are connected to one first upper contact plug;
and
the third upper diffusion layer and the fourth upper diffusion layer are connected to one second upper contact plug.

24 more elements

A semiconductor device comprising:

an element isolation region disposed in a main surface of a semiconductor substrate;
and
a first active region and a second active region which are enclosed by the element isolation region and are adjacent to one another in a first direction, with the interposition of an intermediate element isolation region;
wherein the first active region comprises:
first and second semiconductor pillars which are adjacent to the intermediate element isolation region and are adjacent to one another in a second direction orthogonal to the first direction;
first and second upper diffusion layers located respectively at the top of the first and second semiconductor pillars;
and
a continuous first gate electrode enclosing the peripheries of the first semiconductor pillar and the second semiconductor pillar;
the second active region comprises:
third and fourth semiconductor pillars which are adjacent to the intermediate element isolation region and are adjacent to one another in the second direction orthogonal to the first direction;
third and fourth upper diffusion layers located respectively at the top of the third and fourth semiconductor pillars;
and
a continuous second gate electrode enclosing the peripheries of the third semiconductor pillar and the fourth semiconductor pillar;
and
the intermediate element isolation region comprises:
a dummy pillar extending in the first direction, spanning between the first active region and the second active region;
and
a power-feed gate electrode enclosing the periphery of the dummy pillar;
the first gate electrode and the second gate electrode are each connected to the power-feed gate electrode;
and
the first upper diffusion layer to the fourth upper diffusion layer are connected to one upper contact plug.

18 more elements

Dependencies are inferred from the claim text.

Description13,046 words

Summary1,185 words

#The present invention relates to a semiconductor device, and in particular relates to a semiconductor device provided with vertical transistors.

#In recent years, vertical transistors have been proposed as a technology for miniaturizing transistors. A vertical transistor is a transistor which employs as a channel a semiconductor pillar (base pillar) extending in a direction (Z-direction) perpendicular to the main surface of a semiconductor substrate (the surface on which the transistor is formed, in other words the XY plane defined by the X-direction and the Y-direction).

#More specifically, in a vertical transistor a semiconductor pillar is provided rising from the semiconductor substrate, and a gate electrode is provided at the periphery of the semiconductor pillar, with the interposition of a gate insulating film. A drain region and a drain electrode are provided at the bottom of the semiconductor pillar, and a source region and a source electrode are provided at the top of the semiconductor pillar.

Brief description of the drawings22 figures

#FIG. 1 is a schematic diagram (plan view) illustrating the structure of a semiconductor device according to a first mode of embodiment of the present invention.

#FIG. 2 is a cross-sectional view through the line A-A′ in FIG. 1.

#FIG. 3 is a cross-sectional view through the line B-B′ in FIG. 1.

Detailed description11,402 words

#[First Mode of Embodiment]

#A first mode of embodiment of the present invention will be described in detail with reference to the drawings. In the drawings hereinbelow, the scale and quantity of each component, for example, differ from those of the actual components, in order to facilitate understanding of each component. Further, the arrangement of each component is described by defining an X-Y-Z coordinate system. In this coordinate system, the Z-direction (third direction) is a direction perpendicular to the main surface of a silicon substrate, the X-direction (second direction) is a direction orthogonal to the Z-direction in a plane parallel to the main surface of the silicon substrate, and the Y-direction (first direction) is a direction orthogonal to the X-direction in a plane parallel to the main surface of the silicon substrate. The configuration is the same in the other modes of embodiment.

#(Semiconductor Device)

Facts

Application

14/890,123Filed 8 May 2014

Priority

JP 2013-10042910 May 2013

Published

US 2016/0111362 A121 Apr 2016

Granted

10 Jan 2017

Term ends

8 May 2034

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification15 codes

H10W 20/43
Characterised by their conductive parts: layouts of interconnections
H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs
H10D 30/63
Insulated-gate field-effect transistors [IGFET]: vertical IGFETs
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps

Timeline

10 May 2013Priority claimedJP 2013-100429
8 May 2014Application filedUS 14/890,123
21 Apr 2016PublishedUS 2016/0111362 A1
24 Aug 2016Assigned to Ps5 Luxco S.A.R.L.assignment of assignor's interest
24 Aug 2016Assigned to Longitude Semiconductor S.A.R.L.change of name
10 Jan 2017GrantedUS 9,543,246 B2
21 Aug 2018Assigned to Longitude Licensing Limitedassignment of assignor's interest
12 Oct 2026TodayWithin its term
8 May 2034Term endsEstimated

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims14

Description13,046 words

Drawings

Description13,046 words

Classification15 codes

Life of this patent