Hybrid package transmission line circuits

A packaged integrated circuit (IC), comprising:

• an IC chip electrically coupled to a package substrate, wherein the IC chip includes a RF signal receiver, transmitter, or switch;
• a logic processor electrically coupled to the package substrate;
• and
• an input/output (I/O) bus electrically coupled to the package substrate, wherein the package substrate includes a transmission line circuit that provides a communication link between at least two of:
• the logic processor, the (I/O) bus, and the RF signal receiver or transmitter, and wherein the transmission line circuit further comprises:
• a first trace defining a routing path on a first interconnect level of a package substrate;
• a second trace following the routing path on a second interconnect level of the package substrate separated from the first interconnect level by a first dielectric material disposed there between;
• a plurality of vias extending through the first dielectric material and electrically coupling the first and second traces;
• and
• at least one electrically conductive reference plane separated from at least one of the first and second traces by a second dielectric material disposed there between.

A package substrate, comprising:

• a core having through core vias disposed therein;
• a plurality of build-up layers, each build-up layer comprising an interconnect level and a dielectric layer;
• a bump breakout region formed in one of the interconnect levels;
• and
• a transmission line circuit extending between the bump breakout region and a pair of the through core vias, wherein the transmission line circuit further comprises:
• a first pair of traces defining a balanced signal line routing path between the bump breakout region and the pair of through core vias on a first interconnect level of a package substrate;
• a second pair of traces following the routing path on a second interconnect level of the package substrate separated from the first interconnect level by a first dielectric layer disposed there between;
• a plurality of vias extending through the first dielectric layer and electrically coupling ones of the first pair of traces with ones of the second pair of traces disposed in vertical alignment;
• and
• at least one electrically conductive reference plane separated from at least one of the first and second pair of traces by a second dielectric material disposed there between.