US 9,543,233 B2Granted

Chip package having a dual through hole redistribution layer structure

AssigneeXintec Inc.

InventorsChien-Hung Liu, Ying-Nan Wen, Shih-Yi Lee, Ho-Yin Yiu

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Abstract

A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Claims9

Dependent claims

A chip package, comprising:

a chip having a conductive pad, a first surface, and a second surface opposite to the first surface, wherein the conductive pad is located on the first surface, and the second surface has a first through hole to expose the conductive pad;
a laser stopper located on the conductive pad;
an isolation layer located on the second surface and in the first though hole, and having a third surface opposite to the second surface, wherein the isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole;
a redistribution layer located on the third surface, a sidewall of the second though hole, and the laser stopper that is in the second though hole;
an insulating layer located on the third surface and the redistribution layer, and having an opening for exposing the redistribution layer;
and
a conductive structure located on the redistribution layer that is in the opening of the insulating layer, such that the conductive structure is electrically connected to the conductive pad.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/869,602Filed 29 Sep 2015 · us provisional application
Priority: 12 Nov 2014
Published: US 2016/0133544 A112 May 2016
Granted: 10 Jan 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification35 codes

H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10P 34/42
With high-energy radiation: with electromagnetic radiation, e.g. laser annealing
H10P 50/20
Etching of wafers, substrates or parts of devices: dry etching; Plasma etching; Reactive-ion etching
H10P 52/00
Grinding, lapping or polishing of wafers, substrates or parts of devices