Stacked semiconductor package

A stacked semiconductor package comprising:

• a lower chip;
• and
• an upper chip stacked on the lower chip,
• wherein the lower chip comprises:
• a through electrode area having a first width such that a plurality of through electrodes are disposed along a central axis arranged in a transverse direction of an active surface of the lower chip;
• and
• a function block area that is arranged apart from the through electrode area and in which a plurality of function blocks are disposed,
• wherein the upper chip comprises:
• a pad area disposed along a central axis arranged in a longitudinal direction of the active surface of the upper chip, said pad area having a plurality of pads corresponding to the plurality of through electrodes disposed therein,
• wherein the active surface of the lower chip has a first length measured in a longitudinal direction and a second length measured in a transverse direction,
• wherein a third length measured in the longitudinal direction of the active surface of the upper chip is longer than the second length,
• wherein the first length is greater than the second length, and
• wherein each edge of the function block area has a length that is longer than or equal to half of a difference between the first length and the first width.

A stacked semiconductor package comprising:

• a lower chip having a first through electrode area in which a plurality of through electrodes are disposed, the lower chip having a function block area arranged apart from the first through electrode area and in which a plurality of function blocks are disposed;
• and
• at least one upper chip stacked on the lower chip, said upper chip having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are arranged,
• wherein the pad area is disposed along a central axis of the upper chip,
• wherein an active surface of the lower chip has a first length measured in a longitudinal direction and a second length measured in a transverse direction,
• wherein the first through electrode area extends in the transverse direction, is disposed on a longitudinal side of the lower chip, and has a first width measured in a longitudinal direction,
• wherein the first length is greater than the second length, and
• wherein each edge of the function block area has a length that is longer than or equal to half of a difference between the first length and the first width.