Semiconductor device, semiconductor integrated circuit device, and electronic device

A semiconductor device comprising:

• a semiconductor substrate;
• an active element configured to be formed on the semiconductor substrate;
• and
• a multi-layer wiring structure configured to be formed on the semiconductor substrate;
• wherein the active element includes a diffusion region,
• a wiring layer in the multi-layer wiring structure is electrically connected with a first region in the diffusion region through a via plug,
• a heat dissipation structure is provided in the multi-layer wiring structure, an upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and
• a lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate in a second region different from the first region,
• wherein the multi-layer wiring structure includes a plurality of interlayer insulating films stacked one over another and a plurality of wiring layers, each of the wiring layers includes both a pad and a plurality of via plugs extending downwards from the wiring layer pad as part of the heat dissipation structure making the contact in the second region different from the first region, and the plurality of via plugs of each of the wiring layers are arranged in a two-dimensional matrix form in a plan view, and
• wherein the pad of each of the wiring layers has a plurality of openings formed therethrough, and the openings of the pad in a given one of the wiring layers are situated directly above the openings of the pad in another one of the wiring layers.

A semiconductor integrated circuit device comprising:

• a semiconductor substrate;
• a first function block configured to be formed on a first element forming region on the semiconductor substrate, and to include a first semiconductor element operating at a first frequency;
• a second function block configured to be formed on a second element forming region on the semiconductor substrate, and to include a second semiconductor element operating at a second frequency lower than the first frequency;
• and
• a multi-layer wiring structure configured to be formed on the semiconductor substrate;
• wherein a plurality of interlayer insulating films are stacked one after another in the multi-layer wiring structure,
• the interlayer insulating films include a plurality of wiring layers, respectively,
• a plurality of heat dissipation structures are formed in the multi-layer wiring structure around the first function block, and contact the surface of the semiconductor substrate,
• each of the heat dissipation structures includes a plurality of pad regions and a plurality of via plugs extending downwards from the respective pad regions, one of the pad regions being formed as a part of the corresponding wiring layer in one of the interlayer insulating films, the pad regions being stacked one after another from the interlayer insulating film at a lowest layer to the interlayer insulating film at an uppermost layer,
• the via plugs in each of the interlayer insulating films except for the interlayer insulating film at the lowest layer make contact with the pad region of the underlying interlayer insulating film, and
• the via plugs in the interlayer insulating film at the lowest layer make contact with the surface of the semiconductor substrate outside of the first element forming region, and
• the plurality of via plugs of each of the wiring layers are arranged in a two-dimensional matrix form in a plan view,
• wherein the pad of each of the wiring layers has a plurality of openings formed therethrough, and the openings of the pad in a given one of the wiring layers are situated directly above the openings of the pad in another one of the wiring layers.