Hybrid exposure for semiconductor devices

A semiconductor package comprising:

• a semiconductor die;
• a molding compound encapsulating the semiconductor die, wherein a surface of contact pads of the die are coplanar with a surface of the molding compound;
• and
• a redistribution layer on the semiconductor die and the molding compound, wherein the redistribution layer includes a redistribution line that has a first portion and a second portion, wherein one or more different patterning tools are used to expose the portions of the redistribution line, and wherein sidewalls of the first portion of the redistribution line are not substantially coplanar with sidewalls of the second portion of the redistribution line.

A semiconductor package comprising:

• a semiconductor die;
• a molding compound encapsulating the semiconductor die, wherein a surface of contact pads of the die are coplanar with a surface of the molding compound;
• and
• a redistribution layer on the semiconductor die and the molding compound, wherein the redistribution layer includes a redistribution line that has a first portion and a second portion, wherein one or more different patterning tools are used to expose the portions of the redistribution line, and wherein at least one sidewall of the first portion of the redistribution line is substantially coplanar with at least one sidewall of the second portion of the redistribution line.

A method of forming a semiconductor package, the method comprising:

• encapsulating a semiconductor die with a molding compound, wherein a surface of contact pads of the die are coplanar with a surface of the molding compound;
• applying a dielectric layer on the die and the molding compound, wherein the dielectric layer is applied on the surface of the molding compound that is coplanar with the surface of the contact pads on each of the semiconductor dies;
• applying a seed layer on the dielectric layer;
• applying a resist layer on the seed layer;
• exposing a first portion of the resist layer, wherein the first portion includes a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL;
• and
• exposing a second portion of the resist layer, wherein the second portion includes the second area of the resist layer that includes the electrical communications pathway, wherein the exposed portions of the resist layer are exposed using one or more different patterning tools.