Semiconductor device and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device having a vertical semiconductor device and a horizontal semiconductor device disposed on a single semiconductor substrate,

• the vertical semiconductor device having
• a first semiconductor region of a second conductivity type, the first semiconductor region being selectively disposed in a surface layer of a side of the semiconductor substrate, the surface layer configuring a semiconductor layer of a first conductivity type,
• a second semiconductor region of the first conductivity type, the second semiconductor region being selectively disposed inside the first semiconductor region,
• a first gate insulating film contacting the first semiconductor region at a portion between the semiconductor layer and the second semiconductor region, and
• a first gate electrode contacting the first gate insulating film,
• the horizontal semiconductor device having
• a third semiconductor region of the second conductivity type, the third semiconductor region being selectively disposed in the surface layer and away from the first semiconductor region,
• a fourth semiconductor region of the second conductivity type, the fourth semiconductor region being selectively disposed in the surface layer and away from the first semiconductor region and the third semiconductor region,
• a second gate insulating film, and
• a second gate electrode disposed on a surface of the semiconductor layer, in a portion interposed between the third semiconductor region and the fourth semiconductor region, the second gate electrode being disposed on and contacting the second gate insulating film,
• the method comprising:
• forming the first gate insulating film and the second gate insulating film on said side of the semiconductor substrate;
• forming
• the first gate electrode so as to contact the first gate insulating film, and
• the second gate electrode so as to contact the second gate insulating film;
• after the forming the first gate electrode and the second gate electrode, selectively forming the first semiconductor region in the surface layer so as to contact the first gate insulating film;
• after the forming the first gate electrode and the second gate electrode, forming the third semiconductor region and the fourth semiconductor region in a self-aligning manner at the second gate electrode by ion implantation using the second gate electrode as a mask;
• after the forming the third semiconductor region and the fourth semiconductor region, selectively forming the second semiconductor region inside the first semiconductor region;
• after the forming the second semiconductor region, forming an interlayer dielectric on a principal surface of the semiconductor substrate;
• selectively removing portions of the interlayer dielectric so as to form a plurality of contact holes respectively exposing different corresponding ones of the first semiconductor region, the third semiconductor region, and the fourth semiconductor region;
• respectively forming inside the first semiconductor region, the third semiconductor region, and the fourth semiconductor region by ion implantation through the plurality of contact holes, a first diffusion region that is of the second conductivity type and has an impurity concentration higher than that of the first semiconductor region, a second diffusion region that is of the second conductivity type and has an impurity concentration at least equal to that of the third semiconductor region, and a third diffusion region that is of the second conductivity type and has an impurity concentration at least equal to that of the fourth semiconductor region;
• and
• forming through the plurality of contact holes and after the forming the first diffusion region, the second diffusion region, and the third diffusion region, a plurality of metal wiring layers that are respectively connected to the first diffusion region, the second diffusion region, and the third diffusion region.