Integration of hybrid germanium and group III-V contact epilayer in CMOS
AssigneeGlobalfoundries Inc.
InventorsHiroaki Niimi, Ruilong Xie
Life of this patent
Estimating the term…
Abstract
A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region.
Claims15
A method comprising:
- forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions;
- depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches;
- removing the SiN layer in the PFET region;
- growing a germanium (Ge) epilayer over the source/drain regions in the PFET region;
- depositing metal over the ILD and in the trenches in the NFET and PFET regions;
- etching the metal in the NFET region to expose the conformal SiN layer;
- removing the SiN layer in the NFET region;
- growing a Group III-V epilayer over the source/drain regions in the NFET region;
- and
- depositing metal over the ILD and in the trenches in the NFET region.
A method comprising:
- forming trenches through an interlayer dielectric (ILD) deposited over source/drain regions at opposite sides of metal gates in NFET and PFET regions;
- depositing a conformal silicon nitride (SiN) layer over the metal gates and in the trenches;
- forming a blocking mask over the NFET region, wherein the blocking mask comprises an organic planarization layer (OPL);
- removing the SiN layer in the PFET region;
- removing the blocking mask;
- growing a Ge:B epilayer over the source/drain regions in the PFET region;
- depositing metal over the ILD and in the trenches;
- etching the metal in the NFET region to expose the conformal SiN layer;
- removing the SiN layer in the NFET region;
- growing a Group III-V epilayer over the source/drain regions in the NFET region, the Group III-V epilayer comprising GaAs, InP, InAs, InSb, GaSb, InGaAs, InN or AlGaAs;
- and
- depositing metal over the ILD and in the trenches in the NFET region.
Dependencies are inferred from the claim text.