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US 9,543,213 B2Granted
Asymmetric high-k dielectric for reducing gate induced drain leakage
AssigneeInternational Business Machines Corporation
InventorsAnthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
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Abstract
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
Claims12
A method comprising:
- performing a damaging process on a high-k dielectric sidewall of a gate structure;
- performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region;
- and
- removing the damaged high-k dielectric sidewall to expose underlying sidewalls on the source side, wherein the removing of the damaged high-k dielectric sidewall does not remove a sidewall on the gate structure on the drain side.
1 more element
Dependencies are inferred from the claim text.