Preventing over-polishing of poly gate in metal-gate CMP

An electronic device comprising an electronic component and a semiconductor device electrically connected with the electronic component, the semiconductor device being fabricated by a process comprising the steps of:

• providing a semiconductor substrate containing a front-end device, the front-end device comprising a first gate in a first type transistor region and a second gate in a second type transistor region;
• forming an interlayer dielectric layer on the semiconductor substrate;
• performing a first chemical mechanical polishing (CMP) process having a removal rate of the first and second gates higher than a removal rate of the interlayer dielectric layer on the interlayer dielectric layer so that a surface of the first gate and a surface of the second gate are below a surface of the interlayer dielectric layer after the first CMP process;
• removing a portion of the second gate so that the second gate is lower than the interlayer dielectric layer;
• forming a hard mask layer on the first gate, the second gate and the interlayer dielectric layer;
• removing a portion of the hard mask layer disposed on the first type transistor region;
• removing the first gate by etching using the hard mask layer as a mask to form a trench;
• forming a first work function metal layer in the trench and on the hard mask layer over the second gate;
• forming a metal gate layer on the first work function metal layer;
• and
• forming a metal gate by performing a second CMP process to remove a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer.

A method for manufacturing a semiconductor device, the method comprising:

• providing a semiconductor substrate comprising a front-end device, the front-end device comprising a first gate in a first type transistor region and a second gate in a second type transistor region, the first and second gates comprising a polysilicon material, the second gate being wider than the first gate;
• forming an interlayer dielectric layer on the semiconductor substrate;
• performing a first chemical mechanical polishing (CMP) process on the interlayer dielectric layer to expose a surface of the first gate and a surface of the second gate;
• performing a second CMP process having a removal rate of the first and second gates higher than a removal rate of the interlayer dielectric layer, thereby causing the surface of the first gate and second gate being lower than the surface of the interlayer dielectric layer;
• forming a hard mask layer on the first gate, the second gate, and the interlayer dielectric layer;
• removing a portion of the hard mask layer disposed on the first type transistor region;
• removing the first gate by etching using the hard mask layer as a mask to form a trench;
• forming a first work function metal layer in the trench and on the hard mask layer over the second gate;
• forming a first metal gate layer on the first work function metal layer;
• and
• forming a metal gate by performing a third CMP process to remove a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer, the third CMP process has a high removal rate for the metal gate layer and for the first work function metal layer than for the interlayer dielectric layer, thereby leaving a portion of the first work function metal layer and a portion of the metal gate layer over the second gate;
• performing a fourth CMP process to remove the portion of the first work function metal layer and the portion of the metal gate layer over the second gate, the fourth CMP process has a low polysilicon removal rate to avoid excessive over-polishing of the second gate.