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US 9,543,193 B2Granted
Non-hierarchical metal layers for integrated circuits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLee-Chung Lu, Yuan-Te Hou, Shyue-Shyh Lin, Li-Chun Tien, Dian-Hau Chen
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Abstract
An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch.
Claims20
A method comprising:
- forming a first metal layer comprising:
- forming a first dielectric layer over a semiconductor substrate;
- forming first openings in the first dielectric layer, wherein the first openings are formed using a one-photoresist-one-patterning (1P1E) process;
- and
- filling a first metallic material in the first openings to form first metal lines of the first metal layer;
- and
- forming a second metal layer over the first metal layer, wherein the forming the second metal layer comprises:
- forming a second dielectric layer over the first metal layer;
- forming second openings in the second dielectric layer, wherein two neighboring openings of the second openings are formed using a two-photoresist-two-patterning (2P2E) process, with the two openings ones of the second openings being at a same level;
- and
- filling a second metallic material in the second openings to form second metal lines of the second metal layer.
8 more elements
A method comprising:
- etching a first dielectric layer over a semiconductor substrate to form first openings;
- filling the first openings to form first metal lines, wherein the first metal lines have a first minimum pitch, with the first minimum pitch measured in a first direction perpendicular to lengthwise directions of two of the first metal lines that have the first minimum pitch;
- etching a second dielectric layer over the first dielectric layer to form second openings;
- filling the second openings to form second metal lines, wherein the second metal lines have a second minimum pitch smaller than the first minimum pitch, with the second minimum pitch measured in a second direction perpendicular to lengthwise directions of two of the second metal lines that have the second minimum pitch;
- and
- forming metal vias electrically coupling the first metal lines to the second metal lines.
3 more elements
A method comprising:
- forming a first metal layer over gate electrodes of transistors using two-photoresist-two-patterning (2P2E) processes, wherein first metal lines in the first metal layer has a first minimum pitch;
- forming a second metal layer over the first metal layer using one-photoresist-one-patterning (1P1E) processes, wherein second metal lines in the second metal layer has a second minimum pitch greater than the first minimum pitch;
- and
- forming a third metal layer over the second metal layer using 2P2E processes, wherein third metal lines in the third metal layer has a third minimum pitch smaller than the second minimum pitch.
1 more element
Dependencies are inferred from the claim text.