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US 9,543,192 B2Granted
Stitched devices
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsWei Shao, Juan Boon Tan, Wei Liu, Wanbing Yi
Life of this patent
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Abstract
A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.
Claims20
A method of forming a stitched device comprising:
- providing a wafer having first and second major surfaces, wherein the first major surface includes a photoresist layer, the first major surface includes a stitching level, wherein the stitching level is an interconnect level of the stitched device;
- lithographically processing the stitching level which comprises
- exposing the photoresist layer with an exposure source using a first reticle for the stitching level of a first base device at a first position on the wafer, wherein the first reticle includes a first interconnect pattern for first interconnects of a stitching level of the first base device,
- exposing the photoresist layer with the exposure source using a second reticle for the stitching level of a second base device at a second position on the wafer, wherein the second reticle includes a second interconnect pattern for second interconnects of a stitching level of the second base device, wherein
- adjacent sides of the first and second patterns abut to form common sides of the first and second base device, and
- the first and second interconnect patterns include at least one stitching point for coupling a first stitched interconnect with a second stitched interconnect at the common sides;
- and
- processing the wafer to form first and second interconnects in the stitching levels of the first and second base devices, wherein the first stitched interconnect is electrically coupled to the second stitched interconnect at the stitching point.
5 more elements
A method of forming a stitched device comprising:
- providing a wafer having first and second major surfaces, wherein the first major surface includes a photoresist layer, the first major surface includes a stitching level, wherein the stitching level is an interconnect level of the stitched device;
- lithographically processing the stitching level which comprises
- exposing the photoresist layer with an exposure source using a first reticle for the stitching level of a first base device at a first position on the wafer, wherein the first reticle includes a first interconnect pattern for first interconnects of a stitching level of the first base device,
- exposing the photoresist layer with the exposure source using a second reticle for the stitching level of a second base device at a second position on the wafer, wherein the second reticle includes a second interconnect pattern for second interconnects of a stitching level of the second base device, wherein
- adjacent sides of the first and second patterns abut to form common sides,
- the first and second interconnect patterns include at least one stitching point for coupling a first stitched interconnect with a second stitched interconnect at the common sides, and
- wherein at least one of the first and second stitched interconnects at the stitching point comprises a stitch coupler, the stitch coupler has a larger width than a width of the interconnects;
- and
- processing the wafer to form first and second interconnects in the stitching levels of the first and second base devices, wherein the first stitched interconnect is electrically coupled to the second stitched interconnect at the stitching point.
6 more elements
Dependencies are inferred from the claim text.