US 9,543,188 B2 · Isolation structure, method for manufacturing the same, and semiconductor device having the structure

Abstract

The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device having the structure. The present invention relates to the field of semiconductor manufacture. The isolation structure comprises: a trench embedded in a semiconductor substrate; an oxide layer covering the bottom and sidewalls of the trench, and isolation material in the trench and on the oxide layer, wherein a portion of the oxide layer on an upper portion of the sidewalls of the trench comprises lanthanum-rich oxide. By the trench isolation structure according to the present invention, metal lanthanum in the lanthanum-rich oxide can diffuse into corners of the oxide layer of the gate stack, thus alleviating the impact of the narrow channel effect and making the threshold voltage adjustable.

Claims8

Dependent claims

An isolation structure for a semiconductor device, comprising:

a trench embedded in a semiconductor substrate;
an oxide layer covering a bottom and sidewalls of the trench;
and
isolation material in the trench and on the oxide layer,
wherein only a region of the semiconductor substrate that is adjacent to an upper-half portion of the oxide layer on the sidewalls of the trench is a lanthanum-rich region and only the upper-half portion of the oxide layer on the sidewalls of the trench adjacent to the lanthanum-rich region comprises lanthanum-rich oxide.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/142,378Filed 2 Mar 2011

Priority

CN 2010 1 05400719 Nov 2010

Published

US 2012/0112288 A110 May 2012

Granted

10 Jan 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10W 10/0148
Using trench refilling with dielectric materials, e.g. shallow trench isolations: comprising introducing impurities in side walls or bottom walls…
H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Isolation structure, method for manufacturing the same, and semiconductor device having the structure

Life of this patent

Isolation structure, method for manufacturing the same, and semiconductor device having the structure

Life of this patent

Abstract

Claims8