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US 9,543,044 B2Granted
System and method for improving memory performance and identifying weak bits
AssigneesSTMicroelectronics International N.V., STMicroelectronics S.r.l.
InventorsAbhishek Jain, Andrea Mario Veggetti, Amit Chhabra
Life of this patent
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Abstract
According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.
Claims28
A method for testing a memory, the method comprising:
- receiving an address and a start signal at the memory;
- generating a first detector pulse at a test circuit in response to the start signal, the first detector pulse having a leading edge and a trailing edge;
- detecting a data transition of a bit associated with the address, wherein the bit is a functional bit;
- and
- determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge, wherein detecting the data transition comprises generating a pulse of a specific pulse width when the transition is detected and comparing the generated pulse with the first detector pulse to determine that the data transition occurred after the trailing edge.
2 more elements
A circuit comprising:
- a transition detector circuit configured to be coupled to a data output bus of a memory, wherein the transition detector circuit is configured to detect a transition on any data output bit of the data output bus;
- and
- a clock generator circuit configured to provide a plurality of pulses of different pulse width to the transition detector circuit, wherein the transition detector circuit is further configured to provide a first output signal corresponding to a specific data output bit when a transition is detected on the specific data output bit after a pulse provided by the clock generator circuit, wherein the transition detector circuit comprises pulse generator circuits, each of the pulse generator circuits coupled to a data output bit of the data output bus and having a pulse output, wherein each of the pulse generator circuits is configured to generate a pulse at the pulse output when a transition is detected.
A method for testing a memory, the method comprising:
- providing a first memory clock edge to the memory, wherein the first memory clock edge causes the memory to start writing a data value at a write address within the memory;
- generating a first pulse having a leading edge and a trailing edge in response to the first memory clock edge;
- providing a second memory clock edge to the memory after the trailing edge, wherein the second memory clock edge causes the memory to start reading the data value from the write address within the memory;
- and
- identifying a weak bit at the write address after reading the data value from the write address, wherein the method for testing the memory comprises a sequence comprising the writing of the data value followed by the reading of the data value and followed by the identifying the weak bit, wherein identifying the weak bit comprises
- generating a second pulse having a leading edge and a trailing edge in response to the second memory clock edge,
- detecting a data transition of the bit associated with the write address, and
- determining whether the data transition occurred after the trailing edge of the second pulse, wherein the determining comprises generating a pulse of a specific pulse width when the data transition is detected and comparing the generated pulse with the second pulse to determine that the data transition occurred after the trailing edge of the second pulse.
5 more elements
A method for identifying at least one weakest bit of a plurality of weak bits in a memory, the method comprising:
- providing the memory comprising functional bits and nonfunctional bits, the functional bits comprising the plurality of weak bits;
- applying a first plurality of pulses having a first pulse width to consecutively perform a test operation on each address in the memory and identifying an address in the memory with at least one first weak bit of the plurality of weak bits, wherein the test operation identifies an address as having the at least one first weak bit based on whether a data transition on an output of the memory is detected during a read operation after the duration of the first pulse width, wherein detecting the data transition comprises generating a pulse of a specific pulse width when the transition is detected and comparing the generated pulse with the first pulse width to determine that the data transition occurred after the duration of the first pulse width;
- applying a second plurality of pulses having a second pulse width to consecutively perform the test operation on each address in the memory and identifying an address in the memory with at least one second weak bit of the plurality of weak bits, wherein the test operation identifies an address as having the at least one second weak bit based on whether a data transition on an output of the memory is detected during a read operation after the duration of the second pulse width;
- and
- identifying the at least one weakest bit from the at least one first weak bit, wherein the first pulse width is longer than the second pulse width, wherein the test operation comprises a read-after-write test.
2 more elements
Dependencies are inferred from the claim text.