Semiconductor memory apparatus

A semiconductor memory apparatus comprising:

• a first comparison block configured to compare a plurality of channel data with one another and generate a first comparison signal when at least two channel select signals among a plurality of channel select signals are enabled, and output one of the plurality of channel data as the first comparison signal when only one channel select signal is enabled;
• a second comparison block configured to compare the plurality of channel data and generate a second comparison signal when at least two channel select signals among the plurality of channel select signals are enabled and a channel detection signal is disabled, and output the second comparison signal having a predetermined logic level regardless of the channel data when the channel detection signal is enabled;
• a channel selection detection block configured to enable the channel detection signal when only one channel select signal among the plurality of channel select signals is enabled and disable the channel detection signal when at least two channel select signals among the plurality of channel select signals are enabled;
• and
• a combined output block configured to enable a test result signal when at least one comparison signal of the first and second comparison signals is enabled.