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US 9,543,039 B2Granted
Pulse output circuit, shift register, and display device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsSeiko Amano, Hiroyuki Miyake
Life of this patent
Estimating the term…
Abstract
In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
Claims22
A display device comprising:
- a pixel portion provided on a substrate;
- a driver circuit provided on the substrate,
- wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
- wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
- wherein a gate of the first transistor is electrically connected to a gate of the third transistor,
- wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor,
- wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor through no transistor,
- wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor through no transistor,
- wherein the gate of the first transistor is arranged so that at least a first signal is input,
- wherein the gate of the second transistor is arranged so that at least a second signal is input,
- wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, and
- wherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion.
10 more elements
A display device comprising:
- a pixel portion provided on a substrate;
- a driver circuit provided on the substrate,
- wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
- wherein at least one of the first transistor to the fifth transistor comprises an oxide semiconductor layer comprises a channel formation region,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
- wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
- wherein a gate of the first transistor is electrically connected to a gate of the third transistor,
- wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor,
- wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor through no transistor,
- wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor through no transistor,
- wherein the gate of the first transistor is arranged so that at least a first signal is input,
- wherein the gate of the second transistor is arranged so that at least a second signal is input,
- wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, and
- wherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion.
11 more elements
A shift register comprising:
- a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
- wherein each of the first transistor to the fifth transistor is an n-channel transistor,
- wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
- wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,
- wherein a gate of the first transistor is directly connected to a gate of the third transistor,
- wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor,
- wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor,
- wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor,
- wherein the gate of the first transistor is arranged so that at least a first signal is input,
- wherein the gate of the second transistor is arranged so that at least a second signal is input, and
- wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied.
8 more elements
A shift register comprising:
- a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
- wherein each of the first transistor to the fifth transistor is an n-channel transistor,
- wherein at least one of the first transistor to the fifth transistor comprises an oxide semiconductor layer comprises a channel formation region,
- wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
- wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,
- wherein a gate of the first transistor is directly connected to a gate of the third transistor,
- wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor,
- wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor,
- wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor,
- wherein the gate of the first transistor is arranged so that at least a first signal is input,
- wherein the gate of the second transistor is arranged so that at least a second signal is input, and
- wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied.
9 more elements
A display device comprising:
- a pixel portion;
- and
- a driver circuit,
- wherein the pixel portion and the driver circuit are provided on the same substrate,
- wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
- wherein each of the first transistor to the fifth transistor is an n-channel transistor,
- wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
- wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,
- wherein a gate of the first transistor is directly connected to a gate of the third transistor,
- wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor,
- wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor,
- wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor,
- wherein the gate of the first transistor is arranged so that at least a first signal is input,
- wherein the gate of the second transistor is arranged so that at least a second signal is input, and
- wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied.
12 more elements
A display device comprising:
- a pixel portion;
- and
- a driver circuit,
- wherein the pixel portion and the driver circuit are provided on the same substrate,
- wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
- wherein each of the first transistor to the fifth transistor is an n-channel transistor,
- wherein at least one of the first transistor to the fifth transistor comprises an oxide semiconductor layer comprises a channel formation region,
- wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
- wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,
- wherein a gate of the first transistor is directly connected to a gate of the third transistor,
- wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor,
- wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor,
- wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor,
- wherein the gate of the first transistor is arranged so that at least a first signal is input,
- wherein the gate of the second transistor is arranged so that at least a second signal is input,
- wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, and
- wherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion.
14 more elements
Dependencies are inferred from the claim text.