Non-volatile semiconductor memory device and reading method for non-volatile semiconductor memory device that includes charging of data latch input node prior to latching of sensed data

A reading method of a non-volatile semiconductor memory device having a memory cell, a bit line electrically connected to the memory cell and a sense amplifier electrically connected to the bit line, the sense amplifier including a latch unit configured to hold data read from the memory cell and transmitted through the bit line and a first node, a first transistor having a first end electrically connected to the latch unit and a second end electrically connected to the first node, a second transistor having a first end electrically connected to the first node and a second end electrically connected to the bit line, and a third transistor having a first end electrically connected to a second node between the first end of the first transistor and the latch unit, said method comprising:

• charging the second node to a first voltage by turning on the first transistor for a period of time, and then
• while the first transistor is turned off, charging the first node to a second voltage, turning on the second transistor after charging the first node to the second voltage, and turning on the third transistor after turning on the second transistor.

A reading method of a non-volatile semiconductor memory device having a memory cell, a bit line electrically connected to the memory cell and a sense amplifier electrically connected to the bit line, the sense amplifier including a latch unit configured to hold data read from the memory cell and transmitted through the bit line and a first node, a first transistor having a first end electrically connected to the latch unit and a second end electrically connected to the first node, a second transistor having a first end electrically connected to the first node and a second end electrically connected to the bit line, a third transistor having a gate electrically connected to the first end of the second transistor, and a fourth transistor having a first end electrically connected to the first node and a second end electrically connected to a first end of the third transistor, said method comprising:

• charging a second node between the first end of the first transistor and the latch unit to a first voltage by turning on the first transistor for a period of time, and then
• while the first transistor is turned off, charging the first node to a second voltage, turning on the second transistor after charging the first node to the second voltage, and turning on the fourth transistor after turning on the second transistor.