Memory chip, memory device, and reading method
AssigneeKabushiki Kaisha Toshiba
InventorHiroyuki Nagashima
Life of this patent
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Abstract
A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode.
Claims10
A memory chip comprising:
- a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines;
- and
- a control circuit configured to read data from the memory cell, wherein
- a parameter of the memory chip is set in accordance with an instruction received from a device external to the memory chip,
- the control circuit reads the data from the memory cell in a first read mode when a first parameter is set, and in a second read mode when a second parameter is set, and
- a read mode of the control circuit is maintained as the first read mode or the second read mode until the instruction causes a change in the setting of the parameter.
Dependencies are inferred from the claim text.