Low power high speed program method for multi-time programmable memory device
AssigneeIntegrated Silicon Solution, Inc.
InventorKyoung Chon Jin
Life of this patent
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Abstract
A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.
Claims15
A method for programming a PMOS multi-time programmable (MTP) flash memory cell, the memory cell comprising a select gate transistor connected in series with a floating gate transistor and a control gate capacitively coupled to the gate electrode of the floating gate transistor, the method comprising:
- (a) applying a select gate bias voltage to a control terminal of the select gate transistor to generate a select gate drain current having a first current value;
- (b) applying a control gate bias voltage to the control gate;
- (c) increasing the control gate bias voltage from a first voltage to a second voltage, the second voltage greater than the first voltage;
- (d) sensing a cell current flowing through the memory cell;
- (e) in response to the cell current being less than a cell current limit, stopping the increase of the control gate bias voltage and maintaining the control gate bias voltage;
- (f) sensing the cell current flowing through the memory cell;
- (g) in response to the cell current being greater than the cell current limit, starting to increase the control gate bias voltage from a previous voltage level towards the second voltage;
- and
- (h) repeating from (d) to (g) until the control gate bias voltage reaches the second voltage.
A non-volatile memory device, comprising:
- a two-dimensional array of PMOS multi-time programmable (MTP) flash memory cells, each memory cell being adapted to store one bit of data, each memory cell being accessed by a control gate signal, a select gate signal, a bit-line and a source line, each memory cell comprising a select gate transistor connected in series with a floating gate transistor and a control gate capacitively coupled to the gate electrode of the floating gate transistor;
- a select gate current source configured to generate a first current having a first current value;
- a select gate bias controller configured to generate a select gate bias voltage to be applied to the select gate transistor of a memory cell to be programmed to generate a select gate drain current having the first current value;
- a source line current source configured to generate a second current being a cell current limit;
- a sense amplifier configured to compare a first signal indicative of a program cell current of a memory cell being programmed and a second signal indicative of the cell current limit and to generate an output signal;
- and
- a control gate bias controller configured to generate a control gate bias voltage to be applied to the control gate of the memory cell to be programmed in response to the output signal of the sense amplifier, the control gate bias voltage being increased from a first voltage to a second voltage, the second voltage greater than the first voltage,
- wherein in response to the output signal of the sense amplifier indicating the program cell current being less than the cell current limit, the control gate bias controller stops increasing the control gate bias voltage and maintain the control gate bias voltage;
- and
- wherein in response to the output signal of the sense amplifier indicating the program cell current being greater than the cell current limit, the control gate bias controller increases the control gate bias voltage from a previous voltage level towards the second voltage.
Dependencies are inferred from the claim text.