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US 9,543,015 B1Granted
Memory array and coupled TCAM architecture for improved access time during search operation
AssigneeNXP USA, Inc.
InventorAnirban Roy
Life of this patent
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Abstract
A memory device includes a first ternary content addressable memory (TCAM), a second TCAM, a memory array coupled to the first and second TCAMs, a first priority logic coupled between the first TCAM and the memory array, a second priority logic coupled between the second TCAM and the memory array, and a look-ahead signal generated by the first priority logic and provided to the second priority logic. Match lines from the first and second TCAMs are coupled to respective word lines in the memory array.
Claims20
A memory device comprising:
- a first ternary content addressable memory (TCAM);
- a second TCAM;
- a memory array coupled to the first and second TCAMs;
- a first priority logic coupled between the first TCAM and the memory array;
- a second priority logic coupled between the second TCAM and the memory array;
- and
- a look-ahead signal generated by the first priority logic and provided to the second priority logic, wherein match lines from the first and second TCAMs are coupled to respective word lines in the memory array, and
- wherein a pitch of match lines for the first and second TCAMs is approximately twice a pitch of word lines in the memory array.
5 more elements
A semiconductor device comprising:
- a memory device including:
- a first ternary content addressable memory (TCAM) array;
- a second TCAM array;
- a memory array coupled to the first and second TCAMs;
- an address decode unit coupled to the memory array;
- and
- control circuitry operable to
- set a look-ahead signal to give the first TCAM array higher priority than the second TCAM array during TCAM search operations, and
- disable the address decode unit during TCAM search operations.
6 more elements
A method of operating a memory device comprising:
- enabling a first priority logic unit coupled between a first ternary content addressable memory (TCAM) array and a memory array and enabling a second priority logic unit coupled between a second TCAM array and the memory array while a TCAM search operation is performed on the first and second TCAM arrays;
- and
- disabling an address decode unit in the memory array during the TCAM search operation.
Dependencies are inferred from the claim text.