Multiple layer forming scheme for vertical cross point reram

A method for operating a non-volatile storage system, comprising:

• determining a first group of vertical bit lines connected to a plurality of word line combs, the first group of vertical bit lines includes a first bit line, each word line comb of the plurality of word line combs is connected to the first bit line;
• performing a first forming operation for a first set of non-volatile storage elements connected to the first group of vertical bit lines and the plurality of word line combs, the performing a first forming operation includes setting a first word line comb of the plurality of word line combs to a first voltage and setting a second word line comb of the plurality of word line combs to the first voltage, the first word line comb includes a first finger, the second word line comb includes a second finger, the performing a first forming operation includes setting a first vertical bit line of the first group of vertical bit lines to a second voltage less than the first voltage, the first vertical bit line is connected to the first finger via a first storage element and is connected to the second finger via a second storage element;
• determining a second group of vertical bit lines connected to the plurality of word line combs different from the first group of vertical bit lines, the second group of vertical bit lines includes a second bit line, each word line comb of the plurality of word line combs is connected to the second bit line;
• and
• performing a second forming operation for a second set of non-volatile storage elements connected to the second group of vertical bit lines and the plurality of word line combs, the second forming operation is performed subsequent to the first forming operation.

A non-volatile storage system, comprising:

• a memory array, the memory array includes a first group of vertical bit lines connected to a plurality of word line combs, the first group of vertical bit lines includes a first bit line, each word line comb of the plurality of word line combs is connected to the first bit line, the memory array includes a second group of vertical bit lines connected to the plurality of word line combs, the second group of vertical bit lines includes a second bit line, each word line comb of the plurality of word line combs is connected to the second bit line, the number of vertical bit lines in the second group of vertical bit lines is greater than the number of vertical bit lines in the first group of vertical bit lines;
• and
• one or more control circuits in communication with the memory array, the one or more control circuits cause a first voltage to be applied to a first word line comb of the plurality of word line combs and to a second word line comb of the plurality of word line combs, the first word line comb includes a first finger, the second word line comb includes a second finger, the one or more control circuits cause a second voltage less than the first voltage to be applied to a first vertical bit line of the first group of vertical bit lines, the first vertical bit line is connected to the first finger via a first storage element and is connected to the second finger via a second storage element, the one or more control circuits cause the second voltage to be applied to a second vertical bit line of the second group of vertical bit lines subsequent to applying the second voltage to the first vertical bit line, the second vertical bit line is connected to the first finger via a third storage element and is connected to the second finger via a fourth storage element.