Electronic device having semiconductor storage cells

An electronic device including a semiconductor memory unit, the semiconductor memory unit comprising:

• one or more columns;
• and
• a data line and a data line bar connected with a column selected among the one or more columns, each of the one or more columns including:
• a plurality of storage cells each configured to store 1-bit data, each storage cell including a first variable resistance element which has a first resistance value when a first value is stored therein and a second resistance value when a second value is stored therein and a second variable resistance element which has the second resistance value when the first value is stored therein and the first resistance value when the second value is stored therein;
• a bit line connected to one end of the first variable resistance element;
• a source line connected to the other end of the first variable resistance element;
• a bit line bar connected to one end of the second variable resistance element;
• a source line bar connected to the other end of the second variable resistance element;
• a driving block configured to latch data of the data line and the data line bar when a corresponding column is selected, the driving block configured to, in a write operation, drive the bit line and the source line bar with one voltage of a first voltage and a second voltage, and the source line and the bit line bar with another voltage of the first voltage and the second voltage based on a value of the latched data, and the driving block further configured to, in a read operation, latch data corresponding to a current flowing through the bit line and the bit line bar;
• a first write connection element connected between the bit line and a first end of the driving block driving line, and configured to be turned on in the write operation;
• a second write connection element connected between the source line bar and the first end of the driving block, and configured to be turned on in the write operation;
• a third write connection element connected between the bit line bar and a second end of the driving block, and configured to be turned on in the write operation;
• and
• a fourth write connection element connected between the source line and the second end of the driving block, and configured to be turned on in the write operation.