Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device, comprising:

• a memory layer including a memory cell array;
• a transistor layer including a transistor, the transistor being included in a control circuit that controls the memory cell array;
• and
• a wiring line layer that connects the memory layer and the transistor layer,
• the memory cell array comprising:
• a plurality of first wiring lines arranged in a first direction perpendicular to a principal plane of a substrate;
• a plurality of second wiring lines that are configured so as to extend in the first direction and that intersect the plurality of first wiring lines;
• a plurality of memory cells disposed at intersections of the plurality of first wiring lines and the plurality of second wiring lines, one memory cell including a variable resistance element;
• a third wiring line extending in a second direction, the second direction intersecting the first direction;
• a select transistor connected between the second wiring line and the third wiring line;
• and
• a plurality of select gate lines connected to gates of a plurality of the select transistors aligned in a third direction, the third direction intersecting the first direction and the second direction,
• the wiring line layer comprising:
• a first connecting wiring line connected to a first select gate line of the plurality of select gate lines and extending in the third direction;
• and
• a second connecting wiring line connected to a second select gate line adjacent in the second direction to the first select gate line, and
• the second connecting wiring line comprising:
• a first portion extending in the third direction;
• and
• a second portion extending from the first portion to a layer below the first connecting wiring line.