Write assist circuit integrated with leakage reduction circuit of a static random access memory for increasing the low voltage supply during write operations

A method for providing a low voltage supply for a static random access memory (SRAM), comprising:

• receiving, by a bias transistor, a first input signal at an input terminal of the bias transistor, wherein a first terminal of the bias transistor is connected to a voltage supply line of SRAM cells and a second terminal of the bias transistor is connected to a first reference voltage lower than a second reference voltage of the SRAM cells, the first input signal configuring the bias transistor to maintain the voltage supply line at a first voltage level;
• receiving, by the bias transistor, a power save signal during a power save operation of the SRAM cells, the power save signal configuring the bias transistor to maintain the voltage supply line at a second voltage level higher than the first voltage level,
• receiving, by the bias transistor, a write assist pulse during a write operation of the SRAM cells, the write assist pulse turning off the bias transistor to disconnect the voltage supply line from the first reference voltage;
• receiving, by an input terminal of a write assist circuit, the write assist pulse during the write operation of the SRAM cells;
• responsive to the write assist pulse, increasing the voltage of the voltage supply line of the SRAM cells by the write assist circuit to a third voltage level higher than the first voltage level;
• and
• providing the increased voltage of the voltage supply line to the SRAM cells during the write operation of the SRAM cells.

A non-transitory computer readable storage medium storing a digital representation of a circuit, the circuit comprising:

• a bias transistor having a first terminal, a second terminal, and an input terminal, the first terminal of the bias transistor connected to a voltage supply line of SRAM cells, the second terminal of the bias transistor connected to a first reference voltage lower than a second reference voltage of the SRAM cells, and the input terminal of the bias transistor receiving:
• a power save signal during a power save operation of the SRAM cells, the power save signal turning on the bias transistor to maintain the voltage supply line at a second voltage level higher than the first voltage level,
• a first input signal that configures the bias transistor to connect the voltage supply line to the first reference voltage, thereby maintaining the voltage of the supply line at a first voltage level, and
• a write assist pulse during a write operation of the SRAM cells that turns off the bias transistor to disconnect the voltage supply line from the first reference voltage;
• and
• a write assist circuit having an input terminal and an output terminal, the input terminal of the write assist circuit connected to the input terminal of the bias transistor to receive the write assist pulse, the output terminal of the write assist circuit connected to the voltage supply line of the SRAM cells, the write assist circuit configured to increase a voltage of the voltage supply line to a third voltage level higher than the first voltage level responsive to receiving the write assist pulse during the write operation.