Device with SRAM memory cells including means for polarizing wells of memory cell transistors

A memory device comprising:

• a matrix of memory cells of the SRAM type positioned next one to another while forming several columns of memory cells, each memory cell including transistors forming a memory point, a read port and a write port, wherein:
• the transistors forming the memory point and the write port include a first semiconductor well doped according to a first type of conductivity and the transistors forming the read port include a second semiconductor well doped according to a second type of conductivity opposite the first type of conductivity, or
• the N-type transistors among the transistors of the memory cell include the first well and the P-type transistors among the transistors of the memory cell includes the second well, or
• the N-type transistors among the transistors forming the memory point and the write port include the first well, and the transistors forming the read port and the P-type transistors from among the transistors forming the memory point and the write port include the second well;
• and
• polarization means for the second wells, able to select a value of at least one polarization potential of the second wells and to apply said polarization potential on the second wells, comprising:
• a memory circuit able to store a polarization state of the second wells of the memory cells for each column or group of columns, and
• a selection circuit coupled to the memory circuit, including several inputs on which different polarization potential values are intended to be applied and able to apply, on the second wells of the memory cells of each column or group of columns, one of said polarization potential values selected as a function of the polarization state stored in the memory circuit and associated with said column or said group of columns, wherein the second wells of the memory cells of a same column are formed by a same semiconductor portion doped according to the second type of conductivity, and/or the wherein the first wells of the memory cells of a same column are formed by a same semiconductor portion doped according to the second type of conductivity.

A polarization method for a memory device which includes:

• a matrix of memory cells of the SRAM type positioned next one to another while forming several columns of memory cells, each memory cell including transistors forming a memory point, a read port and a write port, wherein:
• the transistors forming the memory point and the write port include a first semiconductor well doped according to a first type of conductivity and the transistors forming the read port include a second semiconductor well doped according to a second type of conductivity opposite the first type of conductivity, or
• the N-type transistors among the transistors of the memory cell include the first well and the P-type transistors among the transistors of the memory cell includes the second well, or
• the N-type transistors among the transistors forming the memory point and the write port include the first well, and the transistors forming the read port and the P-type transistors from among the transistors forming the memory point and the write port include the second well;
• and
• polarization means for the second wells, able to select a value of at least one polarization potential of the second wells and to apply said polarization potential on the second wells, comprising:
• a memory circuit able to store a polarization state of the second wells of the memory cells for each column or group of columns, and
• a selection circuit coupled to the memory circuit, including several inputs on which different polarization potential values are intended to be applied and able to apply, on the second wells of the memory cells of each column or group of columns, one of said polarization potential values selected as a function of the polarization state stored in the memory circuit and associated with said column or said group of columns, the polarization method for a memory device, comprising:
• storing a polarization state of the second wells of the memory cells for each column or group of columns,
• selecting a value of at least one polarization potential of the second wells as a function of the polarization state stored in the memory circuit and associated with said column or said group of columns, and
• applying said polarization potential on the second wells of said column or said group of columns.