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US 9,542,995 B2Granted
Threshold voltage mismatch compensation sense-amplifiers for static random access memories with multiple differential inputs
AssigneeManoj Sachdev
InventorsManoj Sachdev, Jaspal Singh Shah
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Abstract
Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.
Claims14
A sense amplifier circuit configuration enabling reliable operation, comprising:
- a latch comprising first and second latch node, first and second sensing transistor, first and second load transistor, first and second precharge transistor, first and second column multiplexer transistor, first and second auxiliary sensing transistor serially connected to the first and second sensing transistor, first and second internal node, first and second bitline, an activation transistor;
- and
- first and second bitline signal amplification and boosting means;
- and
- coupling means to selectively couple said first and second latch nodes to said first and second bitlines via said first and second column multiplexer transistor;
- and
- one precharge signal to selectively couple the first and second latch nodes to supply voltage via said first and second precharge transistors;
- and
- one activation signal;
- and a signal delay and signal complementing means to delay and complement said activation signal.
7 more elements
A sense amplifier circuit configuration enabling low-voltage, reliable operation, comprising:
- a latch comprising first and second latch node, first and second sensing transistor, first and second load transistor, first and second precharge transistor, first and second column multiplexer transistor, first and second bitline, an activation transistor;
- and
- first and second bitline signal storage nodes and boosting means;
- and
- coupling means to selectively couple said first and second bitline signal storage nodes to said first and second latch nodes;
- and
- coupling means to selectively couple said first and second latch nodes to said first and second bitlines via said first and second column multiplexer transistor;
- and
- one precharge signal to selectively couple the first and second latch nodes to supply voltage via said first and second precharge transistors;
- and
- one activation signal;
- and a signal delay and signal complementing means to delay and complement said activation signal.
9 more elements
Dependencies are inferred from the claim text.