US 9,542,994 B1 · Retention control in a memory device

Abstract

A memory device and method of operating the memory device are provided. The memory device has bitcells arranged in a plurality of rows and columns. Row driver circuitry provides access to the array of bitcells by selection of an access row of the plurality of rows. The row driver circuitry comprises a retention control latch to store a retention control value and row power gating circuitry responsive to a retention signal to power gate at least one row when the retention control value has a first value and to leave the at least one row powered when the retention control value has a second value. Row-based retention of the content of the bit cells is thus provided, and the leakage current of the memory device when it is in a retention (e.g. sleep) mode, and only some of its rows contain valid data, can thus be reduced.

Claims19

Dependent claims

A memory device comprising:

an array of bitcells arranged in a plurality of rows and a plurality of columns;
and
row driver circuitry to provide access to the array of bitcells by selection of an access row of the plurality of rows,
wherein the row driver circuitry comprises a retention control latch to store a retention control value and row power gating circuitry responsive to a retention signal to power gate at least one row when the retention control value has a first value and to leave the at least one row powered when the retention control value has a second value.

1 more element

Dependencies are inferred from the claim text.

Retention control in a memory device

Life of this patent

Retention control in a memory device

Life of this patent

Abstract

Claims19