Leakage-current abatement circuitry for memory arrays
AssigneeLattice Semiconductor Corporation
InventorLoren McLaury
Life of this patent
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Abstract
In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices.
Claims17
An integrated circuit comprising
- a memory array that comprises:
- one or more sub-arrays, each sub-array comprising a plurality of bit-cells, arranged in rows and columns, bit-cells of each column in each sub-array being coupled to least one bit-line;
- at least one bit-line leakage-current abatement element coupled with each bit-line and configured to inject a current into the bit-line, responsive to a leakage-current reference;
- and
- a bit-line leakage-current reference circuit comprising a transistor, the bit-line leakage-current reference circuit configured to generate the leakage-current reference based on a current in the transistor and to provide the generated leakage-current reference to the at least one bit-line leakage-current abatement element coupled with the bit-line.
Dependencies are inferred from the claim text.