SRAM core cell design with write assist

A memory subsystem, comprising:

• a plurality of static random access memory (SRAM) cells, each SRAM cell comprising:
• a storage unit configured to store a data bit in a storage node,
• an access unit coupled to the storage unit, to a word line, to a bit line and to an inverted bit line and configured to transfer current from the bit line to a first node of the storage unit and from the inverted bit line to a second node of the storage unit when the word line is asserted,
• a row header coupled to the storage unit, to the word line, and to a power supply rail and configured to transfer current from the power supply rail to the storage unit when the word line is not asserted and to transfer substantially no current from the power supply rail to the storage unit when the word line is asserted, and
• a column header coupled to the storage unit, to a write column line, and to the power supply rail and configured to transfer current from the power supply rail to the storage unit when the write column line is not asserted and to transfer substantially no current from the power supply rail to the storage unit when the write column line is asserted;
• wherein the SRAM cell receives an assertion of the write column line prior to receiving an assertion of the word line and the SRAM cell receives a removal of the assertion of the write column line prior to receiving a removal of the assertion of the word line, and the duration of assertion of the write column line is equal to the duration of assertion of the word line;
• and
• a control unit configured to execute a write operation by:
• precharging a bit line and inverted bit line to a high value;
• depending on a value to be written into an SRAM cell, discharging a bit line or inverted bit line associated with the SRAM cell included in the plurality of SRAM cells;
• asserting a write column line associated with the SRAM cell;
• asserting a word line associated with the SRAM cell upon expiration of a first period of time after asserting the write column line;
• unasserting the write column line;
• delaying for a second duration after unasserting the write column line;
• and
• unasserting the word line upon expiration of a second period of time after unasserting the write column line.