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US 9,542,989 B2Granted
Circuit and method for controlling MRAM cell bias voltages
AssigneeEverspin Technologies, Inc.
InventorsDietmar Gogl, Syed M. Alam, Thomas Andre
Life of this patent
Estimating the term…
Abstract
A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
Claims18
A memory, comprising:
- a magnetic memory cell that includes:
- a select transistor having a first terminal, a second terminal, and a gate terminal;
- a memory device having a first terminal and a second terminal, the second terminal of the memory device coupled to the first terminal of the select transistor;
- a replica magnetic memory cell that includes:
- a replica select transistor having a first terminal, a second terminal, and a gate terminal;
- a replica memory device having a first terminal and a second terminal, the second terminal of the replica memory device coupled to the first terminal of the replica select transistor;
- a cell bias control circuit coupled to the magnetic memory cell and the replica magnetic memory cell, the cell bias control circuit configured to:
- apply a word line voltage to the gate terminal of the replica select transistor;
- receive a first feedback voltage corresponding to a voltage at the second terminal of the replica select transistor;
- adjust, using the first feedback voltage, the word line voltage such that a voltage between the gate terminal of the replica select transistor and the voltage at the second terminal of the replica select transistor matches a reference gate-to-source voltage;
- and
- apply the word line voltage to the gate terminal of the select transistor.
9 more elements
A memory, comprising:
- a magnetic memory cell that includes:
- a select transistor having a first terminal, a second terminal, and a gate terminal;
- a memory device having a first terminal and a second terminal, the second terminal of the memory device coupled to the first terminal of the select transistor;
- a replica magnetic memory cell that includes:
- a replica select transistor having a first terminal, a second terminal, and a gate terminal;
- a replica memory device having a first terminal and a second terminal, the second terminal of the replica memory device coupled to the first terminal of the replica select transistor;
- a cell bias control circuit coupled to the magnetic memory cell and the replica magnetic memory cell, the cell bias control circuit configured to:
- generate a first control voltage, wherein the first control voltage controls a voltage at the first terminal of the replica memory device;
- receive a first feedback voltage corresponding to the voltage at the first terminal of the replica memory device;
- receive a second feedback voltage corresponding to a voltage at the second terminal of the replica memory device;
- adjust, using the first and second feedback voltages, the first control voltage such that a voltage across the replica memory device matches a reference memory device voltage;
- and
- use the first control voltage, as adjusted, to control a voltage at the first terminal of the memory device.
10 more elements
A memory, comprising:
- a magnetic memory cell that includes:
- a select transistor having a first terminal, a second terminal, and a gate terminal;
- a memory device having a first terminal and a second terminal, the second terminal of the memory device coupled to the first terminal of the select transistor;
- a replica magnetic memory cell that includes:
- a replica select transistor having a first terminal, a second terminal, and a gate terminal;
- a replica memory device having a first terminal and a second terminal, the second terminal of the replica memory device coupled to the first terminal of the replica select transistor;
- a cell bias control circuit coupled to the magnetic memory cell and the replica magnetic memory cell, the cell bias control circuit configured to:
- generate a first control voltage, wherein the first control voltage controls a voltage at the second terminal of the replica select transistor;
- receive a first feedback voltage corresponding to a voltage at the second terminal of the replica select transistor;
- adjust, using the first feedback voltage, the first control voltage such that the voltage at the second terminal of the replica select transistor matches a reference voltage;
- and
- use the first control voltage, as adjusted, to control a voltage at the second terminal of the select transistor.
9 more elements
Dependencies are inferred from the claim text.