Low power input gating

An integrated circuit, comprising:

• a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal;
• a latch device configured to latch the control input of the memory;
• and
• a latch enable device coupled between the chip enable device and the latch device, wherein the latch enable device is configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory,
• wherein the latch device comprises a low phase latch device.

An integrated circuit, comprising:

• a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal;
• a latch device configured to latch the control input of the memory;
• and
• a latch enable device coupled between the chip enable device and the latch device, wherein the latch enable device is configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory,
• wherein the latch enable device comprises a second logic device coupled to the chip enable device, and wherein the second logic device is configured to receive the clock input signal via the chip enable device based on the chip enable signal.

An integrated circuit, comprising:

• a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal;
• a latch device configured to latch the control input of the memory;
• and
• a latch enable device coupled between the chip enable device and the latch device, wherein the latch enable device is configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory,
• wherein the latch enable device is configured to provide low power input gating to the latch device by using the latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory.

An integrated circuit, comprising:

• a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal;
• a latch device configured to latch the control input of the memory;
• a latch enable device coupled between the chip enable device and the latch device, wherein the latch enable device is configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory;
• and
• a decoder device coupled to the chip enable device, the latch device, and the memory, wherein the decoder device is configured to receive the clock input signal from the chip enable device, receive a latch signal from the latch device, and provide an output signal to the control input of the memory based on the chip enable signal provided to the chip enable device and based on the latch enable signal provided to the latch enable device.

An integrated circuit, comprising:

• a first logic device configured to receive a clock input signal, receive a latch enable signal, and provide a first output clock signal;
• a second logic device configured to receive the first output clock signal and provide a second output clock signal that is a compliment of the first clock input signal;
• and
• a latch device configured to latch a control input of memory based on the first clock output signal, the second clock output signal, and the latch enable signal,
• wherein the first and second logic devices are configured to use the clock input signal to gate the latch device based on the latch enable signal so as to selectively cutoff the clock input signal to the control input of the memory.

A method, comprising:

• receiving multiple signals including a clock input signal, a chip enable signal, and a latch enable signal;
• toggling a control input of memory with the clock input signal based on the chip enable signal;
• latching the control input of the memory with a latch device based on the clock input signal;
• and
• gating the latch device based on a latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory,
• wherein gating the latch device comprises providing low power input gating to the latch device by using the latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory.

A method, comprising:

• receiving multiple signals including a clock input signal, a chip enable signal, and a latch enable signal;
• toggling a control input of memory with the clock input signal based on the chip enable signal;
• latching the control input of the memory with a latch device based on the clock input signal;
• and
• gating the latch device based on a latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory,
• wherein the latch device comprises a low phase latch device.