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US 9,542,972 B1Granted
Systems and methods for multi-head coefficient based scaling
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsAravind Ratnakar Nayak, Lu Lu, Richard Rauschmayer, Haitao Xia
Life of this patent
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Abstract
Systems and method are disclosed relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. One example of the system includes a first equalizer circuit, a second equalizer circuit, a summation circuit, a first multiplication circuit, a second multiplication circuit, and a scalar calculation circuit that is capable of calculating a scalar based upon coefficients that are also provided as inputs to the first equalizer and second equalizer.
Claims20
A data processing system, the system comprising:
- a first equalizer circuit operable to equalize a first data input to yield a first equalized output;
- a first interpolator circuit operable to interpolate a delayed instance of the first data input to yield a first interpolated output;
- a second equalizer circuit operable to equalize a second data input to yield a second equalized output;
- a second interpolated circuit operable to interpolate a delayed instance of the second data input to yield a second interpolated output;
- a first summation circuit operable to sum the first equalized output and the second equalized output to yield a first combined output;
- a data detector circuit operable to apply a data detection algorithm to the first combined output to yield a detected output;
- a first loop pulse estimator circuit operable to estimate a first pulse output from the detected output;
- a second loop pulse estimator circuit operable to estimate a second pulse output from the detected output;
- a first multiplier operable to multiply a first interim feedback by a first scalar value to yield a first scaled output, wherein the first interim feedback is derived from the first pulse output;
- a second multiplier operable to multiply a second interim feedback by a second scalar value to yield a second scaled output, wherein the second interim feedback is derived from the second pulse output;
- and
- a second summation circuit operable to sum a third interim feedback with a fourth interim feedback to yield a second combined output, wherein the third interim feedback is derived from the first interim feedback and the fourth interim feedback is derived from the second interim feedback.
9 more elements
A data processing system, the system comprising:
- a first equalizer circuit operable to equalize a first data input to yield a first equalized output based upon at least in part on a first coefficient;
- a second equalizer circuit operable to equalize a second data input to yield a second equalized output based upon at least in part on a second coefficient;
- a summation circuit operable to sum the first equalized output with the second equalized output to yield a composite output;
- a first multiplication circuit operable to multiply an first input by a first scalar value to yield a first product, wherein the first input is derived from a combination of the composite output and the first data input;
- a second multiplication circuit operable to multiply a second input by a second scalar value to yield a second product, wherein the second input is derived from a combination of the composite output and the second data input;
- and
- a scalar calculation circuit operable to calculate the first scalar based upon the first coefficient and the second coefficient.
4 more elements
A data processing system, the system comprising:
- a first equalizer circuit operable to equalize a first data input to yield a first equalized output;
- a second equalizer circuit operable to equalize a second data input to yield a second equalized output;
- a summation circuit operable to sum the first equalized output with the second equalized output to yield a composite output;
- a first multiplication circuit operable to multiply an first input by a first scalar value to yield a first product, wherein the first input is derived from a combination of the composite output and the first data input;
- a second multiplication circuit operable to multiply a second input by a second scalar value to yield a second product, wherein the second input is derived from a combination of the composite output and the second data input;
- and
- a scalar calculation circuit operable to:
- calculate a mean squared error of the first equalized output to yield a first error;
- calculate a mean squared error of the second equalized output to yield a second error;
- and
- calculate the first scalar based upon the first error and the second error.
8 more elements
Dependencies are inferred from the claim text.