Gate signal line drive circuit and display device

A display device comprising:

• a plurality of pixels arranged in a matrix;
• a plurality of gate signal lines each applying a gate signal to the corresponding pixels;
• a plurality of data signal lines each applying a data signal to the corresponding pixels;
• and
• agate signal line driving circuit outputting the gate signals to the plurality of gate signal lines,
• wherein the gate signal line driving circuit comprises:
• a plurality of shift register basic circuits each of which outputs to the corresponding gate signal line the gate signal which has a high voltage during a high signal period of one screen display period and has a low voltage during a low signal period that is a period other than the high signal period,
• wherein each of the shift register basic circuits comprises:
• a first transistor which is in an ON state in accordance with the high signal period to apply the high voltage to the corresponding gate signal line;
• a second transistor which is in an ON state in accordance with the low signal period to apply the low voltage to the corresponding gate signal line;
• a third transistor which is turned on to apply the low voltage to the corresponding gate signal line in at least apart of a period until the second transistor is turned on after the first transistor is turned off;
• a fourth transistor which applies an OFF voltage to a control electrode of the second transistor in an ON state;
• and
• a fifth transistor which applies an OFF voltage to a control electrode of the fourth transistor,
• wherein an output of a previous stage of the shift register basic circuit is input to both the control electrode of the fourth transistor and a control electrode of the first transistor, and both the fourth transistor and the first transistor are turned on by the output of the previous stage of the shift register basic circuit, and
• wherein the control electrode of the second transistor is electrically connected to the control electrode of the fifth transistor of a subsequent stage of the shift register basic circuit.