Display device including function of reducing luminance gradient

A display device comprising:

• a plurality of pixel units which each includes a light-emitting element and a pixel circuit which supplies the light-emitting element with a drive current, the plurality of pixel units being arranged on a substrate in a matrix;
• a plurality of first scan lines and a plurality of second scan lines each of which is arranged along a row aligned with the pixel unit;
• a plurality of video signal lines each of which is arranged along a column aligned with the pixel unit;
• a plurality of reset power source lines each of which is arranged along the row or the column aligned with the pixel unit;
• a first power source line and a second power source line;
• a scan line drive circuit which sequentially supplies a control signal to the plurality of first scan lines and the plurality of second scan lines and line-sequentially scans the pixel unit in a row unit;
• a signal line drive circuit which supplies the video signal line with a video voltage signal in accordance with the line-sequential scanning;
• and
• a controller which controls a drive operation of the scan line drive circuit and the signal line drive circuit,
• wherein the pixel circuit comprises:
• an output switch including:
• a first terminal electrically connected to the reset power source line, a second terminal electrically connected to the first power source line, and a control terminal electrically connected to the first scan line;
• a drive transistor including a first terminal electrically connected to an anode of the light-emitting element and a second terminal electrically connected to the reset power source line;
• a capacitance electrically connected between a control terminal and the first terminal of the drive transistor;
• and
• a pixel switch including:
• a first terminal electrically connected to the control terminal of the drive transistor, a second terminal electrically connected to the video signal line, a control terminal electrically connected to the second scan line, and the video voltage signal is introduced from the video signal line and is maintained to the capacitance, and
• wherein the controller controls:
• a reset operation which initializes the drive transistor by applying an initialization potential from the video signal line to the control terminal of the drive transistor and by applying a reset potential from the reset power source line to the first terminal of the drive transistor;
• a cancellation operation which cancels a threshold voltage of the drive transistor by passing a current from the first power source line to the drive transistor, in a state where the initialization potential is applied from the video signal line to the control terminal of the drive transistor;
• a correction operation which corrects a mobility of the drive transistor and retains a potential according to the video voltage signal in the capacitance by writing the video voltage signal from the video signal line to the control terminal of the drive transistor through the pixel switch and by passing a current from the first power source line to the drive transistor;
• and
• a light-emitting operation which supplies the light-emitting element with a drive current according to the video voltage signal from the first power source line through the drive transistor,
• the controller deforms a waveform of a control signal which is supplied from the second scan line in a manner that a time of transitioning the pixel switch from an on-state to an off-state is longer than a time of transitioning the pixel switch from the on-state to the off-state by a non-deformed control signal, when writing the video voltage signal in the correction operation, and
• a ratio (W/L) of a channel width (W) and a channel length (L) of a second buffer transistor, which outputs a control signal supplied from the second scan line to transition the pixel switch from the on-state to the off-state in the correction operation, is smaller than a ratio (W/L) of a channel width (W) and a channel length (L) of a first buffer transistor, which outputs a control signal supplied from the second scan line to transition the pixel switch from the on-state to the off-state in the reset operation and the cancellation operation.