Efficient hardware implementation of spiking networks
AssigneeQUALCOMM Incorporated
InventorsJeffrey Alexander Levin, Venkat Rangan, Erik Christopher Malone
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Abstract
Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.
Claims44
A method for operating an artificial nervous system with a plurality of artificial neurons, comprising:
- operating simultaneously multiple super neuron processing units in the artificial nervous system for updating states of the artificial neurons, wherein a subset of the artificial neurons is assigned to each super neuron processing unit;
- interfacing the super neuron processing units with a memory;
- and
- accessing synaptic weights and plasticity parameters of the artificial nervous system stored in the memory, wherein organization of the memory allows contiguous memory access.
An apparatus for operating an artificial nervous system with a plurality of artificial neurons, comprising:
- a first circuit configured to operate simultaneously multiple super neuron processing units in the artificial nervous system for updating states of the artificial neurons, wherein a subset of the artificial neurons is assigned to each super neuron processing unit;
- a second circuit configured to interface the super neuron processing units with a memory;
- and
- a third circuit for accessing stored synaptic weights and plasticity parameters of the artificial nervous system stored in the memory, wherein organization of the memory allows contiguous memory access.
An apparatus for operating an artificial nervous system with a plurality of artificial neurons, comprising:
- means for operating simultaneously multiple super neuron processing units in the artificial nervous system for updating states of the artificial neurons, wherein a subset of the artificial neurons is assigned to each super neuron processing unit;
- means for interfacing the super neuron processing units with a memory;
- and
- means for accessing synaptic weights and plasticity parameters of the artificial nervous system stored in the memory, wherein organization of the memory allows contiguous memory access.
A non-transitory computer-readable medium for operating an artificial nervous system with a plurality of artificial neurons, the non-transitory computer-readable medium having instructions executable to:
- operate simultaneously multiple super neuron processing units in the artificial nervous system for updating states of the artificial neurons, wherein a subset of the artificial neurons is assigned to each super neuron processing unit;
- interface the super neuron processing units with a memory;
- and
- access synaptic weights and plasticity parameters of the artificial nervous system stored in the memory, wherein organization of the memory allows contiguous memory access.
Dependencies are inferred from the claim text.