Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction

A method of performing static timing analysis, said method comprising:

• accessing a memory that stores an integrated circuit design that is partitioned into multiple hierarchical entities;
• identifying multiple signal pathways in a hierarchical entity selected for analysis from amongst said multiple hierarchical entities, said multiple signal pathways comprising at least a first signal pathway;
• determining an internal timing constraint of a specific logic device in said first signal pathway based on a known reference value;
• deriving a first boundary timing constraint associated with said first signal pathway based on said internal timing constraint;
• deriving a second boundary timing constraint associated with said first signal pathway based on said first boundary timing constraint and a target slack value for said internal timing constraint, said first boundary timing constraint and said second boundary timing constraint are boundaries of valid timing signals for said hierarchical entity;
• performing a static timing analysis of said hierarchical entity using said second boundary timing constraint;
• making design adjustments to said hierarchical entity based on results of said static timing analysis;
• iteratively repeating said determining of said internal timing constraint, said deriving of said first boundary timing constraint, said deriving of said second boundary timing constraint, said performing of said static timing analysis, and said making of said design adjustments in order to minimize overlap between victim and aggressor timing windows prior to generating an overall signal timing model for said integrated circuit design;
• and
• generating a timing abstraction for said hierarchical entity based on said static timing analysis, multiple ones of said timing abstraction being used to analyze said overall signal timing model for said integrated circuit design.

A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, said program instructions being executable by a computer to cause said computer to perform a method for static timing analysis, said method comprising:

• accessing a memory that stores an integrated circuit design that is partitioned into multiple hierarchical entities;
• identifying multiple signal pathways in a hierarchical entity selected for analysis from amongst said multiple hierarchical entities, said multiple signal pathways comprising at least a first signal pathway;
• determining an internal timing constraint of a specific logic device in said first signal pathway based on a known reference value;
• deriving a first boundary timing constraint associated with said first signal pathway based on said internal timing constraint;
• deriving a second boundary timing constraint associated with said first signal pathway based on said first boundary timing constraint and a target slack value for said internal timing constraint, said first boundary timing constraint and said second boundary timing constraint are boundaries of valid timing signals for said hierarchical entity;
• performing a static timing analysis of said hierarchical entity using said second boundary timing constraint;
• making design adjustments to said hierarchical entity based on results of said static timing analysis;
• iteratively repeating said determining of said internal timing constraint, said deriving of said first boundary timing constraint, said deriving of said second boundary timing constraint, said performing of said static timing analysis, and said making of said design adjustments in order to minimize overlap between victim and aggressor timing windows prior to generating an overall signal timing model for said integrated circuit design;
• and
• generating a timing abstraction for said hierarchical entity based on said static timing analysis, multiple ones of said timing abstraction being used to analyze said overall signal timing model for said integrated circuit design.