Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
AssigneeSypherMedia International, Inc.
InventorsBryan Jason Wang, Lap Wai Chow, James Peter Baukus, Ronald Paul Cocchi
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Abstract
A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.
Claims34
A computer-implemented method of camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, the method comprising the steps of:
- identifying, using the computer, at least one gap between the plurality of interconnected functional logic cells having no functional logic therein;
- placing, using the computer, one filler cell or combination of filler cells into the identified gap, wherein at least one of the filler cells has a physical design layout similar to but different from at least one of the functional logical cells;
- and
- defining, using the computer, a routing of the placed one filler cell or combination of filler cells;
- wherein the placed one filler cell or routed combination of filler cells camouflages the interconnected functional logic cells and the placed one filler cell or combination of filler cells perform none of the one or more ASIC logical functions.
An application specific integrated circuit (ASIC) having a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions and camouflaging, the camouflaging defined by performing steps comprising:
- identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein;
- placing one filler cell or combination of filler cells into the identified gap, wherein at least one of the filler cells has a physical design layout similar to but different from at least one of the functional logical cells;
- and
- defining a routing of the placed one filler cell or combination of filler cells;
- wherein the placed one filler cell or routed combination of filler cells camouflages the interconnected functional logic cells and the placed one filler cell or combination of filler cells perform none of the one or more ASIC logical functions.
Dependencies are inferred from the claim text.