Generating a parallel data signal by converting serial data of a serial data signal to parallel data

A method of generating a parallel data signal by converting serial data of a serial data signal to parallel data, the parallel data signal including one of:

• eight bits of parallel data and ten bits of parallel data, the method comprising:
• generating based on a half rate clock, by a logic divider of the deserializer, a quarter rate clock, a mode rate clock, and a selection control signal;
• wherein the mode rate clock is aligned to the quarter rate clock such that each positive edge of the mode rate clock occurs between a negative edge of the quarter rate clock and the next consecutive positive edge of the quarter rate clock which follows the negative edge of the quarter rate clock;
• wherein the mode rate clock is aligned to the selection control signal such that the positive edge of the mode rate clock is after a negative edge of the quarter rate clock and before the next consecutive edge of the selection control signal which follows the negative edge of the quarter rate clock;
• generating, by a first set of latches, an output including sampling and aligning, the serial data from the serial data signal into the deserializer circuit based on the half rate clock;
• latching based on the quarter rate clock, by a second set of latches of a shift register of the deserializer, the output of the first set of latches;
• and
• outputting, by multiplexer logic of the deserializer, the parallel data signal including latching data from the shift register,
• wherein data is latched into the second set of latches in the shift register such that the first ten bits of a particular data sequence of the serial data are available during an entire clock cycle of the quarter rate clock and that the next two bits of the particular data sequence are available for only a second half of a cycle of the quarter rate clock.

A deserializer circuit for generating a parallel data signal by converting serial data of a serial data signal to parallel data, the parallel data signal including one of:

• eight bits of parallel data and ten bits of parallel data, the deserializer circuit including:
• a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal;
• wherein the mode rate clock is aligned to the quarter rate clock such that each positive edge of the mode rate clock occurs between a negative edge of the quarter rate clock and the next consecutive positive edge of the quarter rate clock which follows the negative edge of the quarter rate clock;
• wherein the mode rate clock is aligned to the selection control signal such that the positive edge of the mode rate clock is after a negative edge of the quarter rate clock and before the next consecutive edge of the selection control signal which follows the negative edge of the quarter rate clock;
• a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock;
• a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider;
• and
• multiplexer logic configured to output the parallel data signal including latching data from the shift register.